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BR24G24FVT-3 Datasheet(PDF) 3 Page - Rohm |
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BR24G24FVT-3 Datasheet(HTML) 3 Page - Rohm |
3 / 36 page Datasheet 3/33 BR24G32-3 TSZ02201-0R2R0G100210-1-2 29.Mar.2013 Rev.003 ©2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 www.rohm.com AC Characteristics (Unless otherwise specified, Ta=-40°C to +85°C, VCC=1.6V to 5.5V) Parameter Symbol Limit Unit Min Typ Max Clock Frequency fSCL - - 400 kHz Data Clock High Period tHIGH 0.6 - - µs Data Clock Low Period tLOW 1.2 - - µs SDA, SCL (INPUT) Rise Time (1) tR - - 1.0 µs SDA, SCL (INPUT) Fall Time (1) tF1 - - 1.0 µs SDA (OUTPUT) Fall Time (1) tF2 - - 0.3 µs Start Condition Hold Time tHD:STA 0.6 - - µs Start Condition Setup Time tSU:STA 0.6 - - µs Input Data Hold Time tHD:DAT 0 - - ns Input Data Setup Time tSU:DAT 100 - - ns Output Data Delay Time tPD 0.1 - 0.9 µs Output Data Hold Time tDH 0.1 - - µs Stop Condition Setup Time tSU:STO 0.6 - - µs Bus Free Time tBUF 1.2 - - µs Write Cycle Time tWR - - 5 ms Noise Spike Width (SDA and SCL) tI - - 0.1 µs WP Hold Time tHD:WP 1.0 - - µs WP Setup Time tSU:WP 0.1 - - µs WP High Period tHIGH:WP 1.0 - - µs (1) Not 100% TESTED. Condition Input data level:VIL=0.2×VCC VIH=0.8×VCC Input data timing reference level: 0.3×VCC/0.7×VCC Output data timing reference level: 0.3×VCC/0.7×VCC Rise/Fall time : ≦20ns Serial Input / Output Timing ○Input read at the rise edge of SCL ○Data output in sync with the fall of SCL Figure 2-(a). Serial Input / Output Timing Figure 2-(b). Start-Stop Bit Timing Figure 2-(c). Write Cycle Timing Figure 2-(d). WP Timing at Write Execution Figure 2-(e). WP Timing at Write Cancel 70% 70% tSU:STA tHD:STA START CONDITION tSU:STO STOP CONDITION 30% 30% 70% 70% D0 ACK tWR write data (n-th address) START CONDITION STOP CONDITION 70% 70% DATA(1) D0 ACK D1 DATA(n) ACK tWR 30% 70% STOP CONDITION tHD:WP tSU:WP 30% 70% DATA(1) D0 D1 ACK DATA(n) ACK tHIGH:WP 70% 70% tWR 70% SCL SDA (入力) SDA (出力) tR tF1 tHIGH tSU:DAT tLOW tHD:DAT tDH tPD tBUF tHD:STA 70% 30% 70% 70% 30% 70% 70% 30% 30% 70% 70% 30% 70% 70% 70% 70% 30% 30% 30% 30% tF2 (INPUT) (OUTPUT) |
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