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UCC3818DWG4 Datasheet(PDF) 10 Page - Texas Instruments |
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UCC3818DWG4 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 32 page UCC2817, UCC2818, UCC3817, UCC3818 BiCMOS POWER FACTOR PREREGULATOR SLUS395J - FEBRUARY 2000 - REVISED MARCH 2009 10 www.ti.com APPLICATION INFORMATION multiplier (continued) The IIAC signal is obtained through a high-value resistor connected between the rectified ac line and the IAC pin of the UCC3817/18. This resistor (RIAC) is sized to give the maximum IIAC current at high line. For the UCC3817/18 the maximum IIAC current is about 500 µA. A higher current than this can drive the multiplier out of its linear range. A smaller current level is functional, but noise can become an issue, especially at low input line. Assuming a universal line operation of 85 VRMS to 265 VRMS gives a RIAC value of 750 kΩ. Because of voltage rating constraints of standard 1/4-W resistor, use a combination of lower value resistors connected in series to give the required resistance and distribute the high voltage amongst the resistors. For this design example two 383-k Ω resistors were used in series. The current into the IAC pin is mirrored internally to the VFF pin where it is filtered to produce a voltage feed forward signal proportional to line voltage. The VFF voltage is used to keep the power stage gain constant; and to provid input power limiting. Please refer to Texas Instruments application note SLUA196 for detailed explanation on how the VFF pin provides power limiting. The following equation can be used to size the VFF resistor (RVFF) to provide power limiting where VIN(min) is the minimum RMS input voltage and RIAC is the total resistance connected between the IAC pin and the rectified line voltage. R VFF + 1.4 V V IN(min) 0.9 2 R IAC [ 30 kW Because the VFF voltage is generated from line voltage it needs to be adequately filtered to reduce total harmonic distortion caused by the 120 Hz rectified line voltage. Refer to Unitrode Power Supply Design Seminar, SEM−700 Topic 7, [Optimizing the Design of a High Power Factor Preregulator.] A single pole filter was adequate for this design. Assuming that an allocation of 1.5% total harmonic distortion from this input is allowed, and that the second harmonic ripple is 66% of the input ac line voltage, the amount of attenuation required by this filter is: 1.5 % 66 % + 0.022 With a ripple frequency (fR) of 120 Hz and an attenuation of 0.022 requires that the pole of the filter (fP) be placed at: f P + 120 Hz 0.022 [ 2.6 Hz The following equation can be used to select the filter capacitor (CVFF) required to produce the desired low pass filter. C VFF + 1 2 p R VFF f P [ 2.2 mF The RMOUT resistor is sized to match the maximum current through the sense resistor to the maximum multiplier current. The maximum multiplier current, or IMOUT(max), can be determined by the equation: I MOUT(max) + I IAC @V IN(min) V VAOUT(max) * 1V K V VFF 2 (min) |
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