February 17, 2010 S71PL-J_00_B6

S71PL-J Based MCPs

11

Data

She e t

4.

Pin Description

5.

Logic Symbol

Signal

Description

A21–A0

22 Address Inputs (Common)

DQ15–DQ0

16 Data Inputs/Outputs (Common)

CE1#f

Chip Enable 1 (Flash)

CE#f2

Chip Enable 2 (Flash)

CE1#ps

Chip Enable 1 (pSRAM)

CE2ps

Chip Enable 2 (pSRAM)

OE#

Output Enable (Common)

WE#

Write Enable (Common)

RY/BY#

Ready/Busy Output (Flash 1)

UB#

Upper Byte Control (pSRAM)

LB#

Lower Byte Control (pSRAM)

RESET#

Hardware Reset Pin, Active Low (Flash 1)

WP#/ACC

Hardware Write Protect/Acceleration Pin (Flash)

Flash 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances)

pSRAM Power Supply

Device Ground (Common)

NC

Pin Not Connected Internally

22

16

DQ15–DQ0

A21–A0

CE1#f

OE#

WE#

RES ET#

R Y/BY#

WP #/ACC

UB#

CE2#f

CE2ps

CE1#ps

LB#