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RC28F128J3C-150 Datasheet(PDF) 9 Page - Intel Corporation |
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RC28F128J3C-150 Datasheet(HTML) 9 Page - Intel Corporation |
9 / 72 page 28F256J3, 28F128J3, 28F640J3, 28F320J3 Datasheet 9 suspended (and programming is inactive), program is suspended, or the device is in reset/power- down mode. Additionally, the configuration command allows the STS signal to be configured to pulse on completion of programming and/or block erases. Three CE signals are used to enable and disable the device. A unique CE logic design (see Table 13, “Chip Enable Truth Table” on page 33) reduces decoder logic typically required for multi-chip designs. External logic is not required when designing a single chip, a dual chip, or a 4- chip miniature card or SIMM module. The BYTE# signal allows either x8 or x16 read/writes to the device. BYTE#-low selects 8-bit mode; address A0 selects between the low byte and high byte. BYTE#-high enables 16-bit operation; address A1 becomes the lowest order address and address A0 is not used (don’t care). A device block diagram is shown in Figure 4 on page 14. When the device is disabled (see Table 13 on page 33), with CEx at VIH and RP# at VIH, the standby mode is enabled. When RP# is at VIL, a further power-down mode is enabled which minimizes power consumption and provides write protection during reset. A reset time (tPHQV) is required from RP# going high until data outputs are valid. Likewise, the device has a wake time (tPHWL) from RP#-high until writes to the CUI are recognized. With RP# at VIL, the WSM is reset and the Status Register is cleared. 2.1 Block Diagram Figure 1. 3 Volt Intel StrataFlash® Memory Block Diagram 32-Mbit: Thirty-two 64-Mbit: Sixty-four 128-Mbit: One-hundred twenty-eight 128-Kbyte Blocks Input Buffer Y-Gating Program/Erase Voltage Switch Data Comparator Status Register Identifier Register I/O Logic Address Latch Address Counter X-Decoder Y-Decoder Input Buffer Output Buffer GND VCC VPEN CE0 CE1 CE2 WE# OE# RP# BYTE# Command User Interface A[MAX:MIN] D[15:0] VCC Write State Machine Multiplexer Query STS VCCQ CE Logic A[2:0] |
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