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74LCX573MTCX-NL3 Datasheet(PDF) 2 Page - Fairchild Semiconductor |
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74LCX573MTCX-NL3 Datasheet(HTML) 2 Page - Fairchild Semiconductor |
2 / 14 page 2 www.fairchildsemi.com 74LCX573 Rev. 2.0.0 Logic Symbol Connection Diagrams Pin Assignments for SOIC, SOP, SSOP, TSSOP Pad Assignments for DQFN (Top View) Pin Descriptions Truth Table H = HIGH Voltage L = LOW Voltage Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable Functional Description The LCX573 contains eight D-type latches with 3-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are enabled. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. D0 D1 D2 D3 D4 D5 D6 D7 O0 OE LE O1 O2 O3 O4 O5 O6 O7 D1 D2 D3 D4 D5 D6 D7 GND D0 O1 O2 O3 O4 O5 O6 O7 O0 LE VCC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 OE D1 D2 D3 D4 D5 D6 D7 GND D0 O1 O2 O3 O4 O5 O6 O7 LE O0 VCC 120 2 3 4 5 6 7 8 9 10 11 19 18 17 16 15 14 13 12 OE Pin Names Description D0–D7 Data Inputs LE Latch Enable Input OE 3-STATE Output Enable Input O0–O7 3-STATE Latch Outputs Inputs Outputs OE LE D On LH H H LH L L LL X O0 HX X Z Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. D0 O0 D Q LE LE OE D1 O1 D Q LE D2 O2 D Q LE D3 O3 D Q LE D4 O4 D Q LE D5 O5 D Q LE D6 O6 D Q LE D7 O7 D Q LE |
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