2

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74LCX573 Rev. 2.0.0

Logic Symbol

Connection Diagrams

Pin Assignments for

SOIC, SOP, SSOP, TSSOP

Pad Assignments for DQFN

(Top View)

Pin Descriptions

Truth Table

H = HIGH Voltage

L = LOW Voltage

Z = High Impedance

X = Immaterial

Enable

Functional Description

The LCX573 contains eight D-type latches with 3-STATE

output buffers. When the Latch Enable (LE) input is

condition the latches are transparent, i.e., a latch output

will change state each time its D input changes. When

LE is LOW the latches store the information that was

present on the D inputs a setup time preceding the

HIGH-to-LOW transition of LE. The 3-STATE buffers are

controlled by the Output Enable (OE) input. When OE is

LOW, the buffers are enabled. When OE is HIGH the

buffers are in the high impedance mode but this does not

interfere with entering new data into the latches.

OE

LE

GND

LE

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

OE

GND

LE

120

2

3

4

5

6

7

8

9

10

11

19

18

17

16

15

14

13

12

OE

Pin Names

Description

Data Inputs

LE

Latch Enable Input

OE

3-STATE Output Enable Input

3-STATE Latch Outputs

Inputs

Outputs

OE

LE

D

LH

H

H

LH

L

L

LL

X

HX

X

Z

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate

propagation delays.

D

Q

LE

LE

OE

D

Q

LE

D

Q

LE

D

Q

LE

D

Q

LE

D

Q

LE

D

Q

LE

D

Q

LE