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74LCX373 Datasheet(PDF) 2 Page - Fairchild Semiconductor |
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74LCX373 Datasheet(HTML) 2 Page - Fairchild Semiconductor |
2 / 15 page 2 www.fairchildsemi.com 74LCX373 Rev. 2.0.0 Logic Symbols Connection Diagrams Pin Assignments for SOIC, SOP, SSOP, TSSOP Pad Assignments for DQFN (Top View) Pin Descriptions Truth Table H = HIGH Voltage L = LOW Voltage Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable Functional Description The LCX373 contains eight D-type latches with 3-STATE standard outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE standard outputs are controlled by the Output Enable (OE) input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. D0 D1 D2 D3 D4 D5 D6 D7 O0 OE LE O1 O2 O3 O4 O5 O6 O7 IEEE/IEC O0 OE LE EN C1 1D D0 O1 D1 O2 D2 O3 D3 O4 D4 O5 D5 O6 D6 O7 D7 D0 D1 O1 O2 D2 D3 O3 GND O0 D7 D6 O6 O5 D5 D4 O4 O7 LE VCC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 OE D0 D1 O1 O2 D2 D3 O3 GND O0 D7 D6 O6 O5 D5 D4 O4 LE O7 VCC 120 2 3 4 5 6 7 8 9 10 11 19 18 17 16 15 14 13 12 OE Pin Names Description D0–D7 Data Inputs LE Latch Enable Input OE 3-STATE Output Enable Input O0–O7 3-STATE Latch Outputs Inputs Outputs LE OE Dn On XH X Z HL L L HL H H LL X O0 |
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