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ATxmega32A4U-AU Datasheet(PDF) 9 Page - ATMEL Corporation |
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ATxmega32A4U-AU Datasheet(HTML) 9 Page - ATMEL Corporation |
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9 / 121 page  9 8387A–AVR–07/11 XMEGA A4U tion is pre-fetched from the Program Memory. This enables instructions to be executed in every clock cycle. The program memory is In-System Self-Programmable Flash memory. 6.3 ALU - Arithmetic Logic Unit The Arithmetic Logic Unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed. The ALU operates in direct connection with all the 32 general purpose registers. In a single clock cycle, arithmetic operations between general purpose registers or between a register and an immedi- ate are executed and the result is stored back in the Register File. After an arithmetic or logic operation, the Status Register is updated to reflect information about the result of the operation. The ALU operations are divided into three main categories – arithmetic, logical, and bit-func- tions. Both 8- and 16-bit arithmetic is supported, and the instruction set allows for efficient implementation of 32-bit arithmetic. The hardware multiplier supports signed and unsigned mul- tiplication and fractional format. 6.4 Program Flow After reset, the CPU starts to execute instructions from the lowest address in the Flash Program Memory ‘0’. The Program Counter (PC) addresses the next instruction to be fetched. After a reset, the PC is set to location ‘0’. Program flow is provided by conditional and unconditional jump and call instructions, capable of addressing the whole address space directly. Most AVR instructions use a 16-bit word format, while a limited number uses a 32-bit format. During interrupts and subroutine calls, the return address PC is stored on the Stack. The Stack is allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. After reset the Stack Pointer (SP) points to the highest address in the internal SRAM. The SP is read/write accessible in the I/O memory space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR CPU. 6.5 Register File The Register File consists of 32 x 8-bit general purpose working registers with single clock cycle access time. The Register File supports the following input/output schemes: • One 8-bit output operand and one 8-bit result input • Two 8-bit output operands and one 8-bit result input • Two 8-bit output operands and one 16-bit result input • One 16-bit output operand and one 16-bit result input Six of the 32 registers can be used as three 16-bit address register pointers for data space addressing - enabling efficient address calculations. One of these address pointers can also be used as an address pointer for look up tables in Flash program memory. |
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