NJG1695ME7

- 10 -

I

TEST PCB LAYOUT

(TOP VIEW)

<PCB LAYOUT GUIDELINE>

PRECAUTIONS

[1] The DC current at RF ports must be equal to zero, which can be achieved with DC blocking capacitors

(C1~C10).

(However, in case there is no possibility that DC current flows, the DC blocking capacitors are unnecessary, i.e.

the RF signals are fed by SAW filters that block DC current by nature, etc.)

[2] To reduce stripline influence on RF characteristics, please locate the bypass capacitor (C11) close to VDD

terminal.

[3] For good isolation, the GND terminals must be connected to the PCB ground plane of substrate, and the

through-holes connecting the backside ground plane should be placed near by the pin connection.

PCB:

FR-4, t=0.2mm

Capacitor Size:

0603, 1005

Strip Line Width:

0.4mm

PCB Size:

53 x 40mm

C1

C2

C3

C4

C5 C6

C7

C8

C9

C10

C11

PCA

PCB

P1B

P1A

P2A

P2B

P3B

P3A

P4B

P4A

Paths

Frequency

(GHz)

Loss

(dB)

1.0

0.50

2.0

0.84

PCA-P1A,

PCB-P1B,

PCA-P3A,

PCB-P3B

2.7

1.10

1.0

0.46

2.0

0.77

PCA-P2A,

PCB-P2B,

PCA-P4A,

PCB-P4B

2.7

0.97

Losses of PCB, capacitors and connectors

1

2

3

4

5

14

13

12

11

10

6

7

8

9

18

17

16

15

PCB Pattern

Through-hole (radius: 0.15mm)

Pin

Note2:

The ground plane and the through-holes under Tab, as shown

in the picture, are not necessities. There is no problem in

deleting them in the practical PCB design, though in such case

beware that the GND terminals (pin 10 and 14 as for this

particular design shown in the picture) still need through-holes

being located in their vicinities.