© 2000 Fairchild Semiconductor Corporation

DS009469

www.fairchildsemi.com

April 1988

Revised September 2000

74F74

Dual D-Type Positive Edge-Triggered Flip-Flop

General Description

The F74 is a dual D-type flip-flop with Direct Clear and Set

inputs and complementary (Q, Q) outputs. Information at

the input is transferred to the outputs on the positive edge

of the clock pulse. Clock triggering occurs at a voltage level

of the clock pulse and is not directly related to the transition

time of the positive-going pulse. After the Clock Pulse input

threshold voltage has been passed, the Data input is

locked out and information present will not be transferred to

the outputs until the next rising edge of the Clock Pulse

input.

Asynchronous Inputs:

Clear and Set are independent of clock

makes both Q and Q HIGH

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

IEEE/IEC

Connection Diagram

Order Number

Package Number

Package Description

74F74SC

M14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

74F74SJ

M14D

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74F74PC

N14A

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide