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XTR110AD Datasheet(PDF) 7 Page - Texas Instruments |
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XTR110AD Datasheet(HTML) 7 Page - Texas Instruments |
7 / 19 page XTR110 7 SBOS141C www.ti.com If the supply voltage, +VCC, exceeds the gate-to-source breakdown voltage of QEXT, and the output connection (drain of QEXT) is broken, QEXT could fail. If the gate-to- source breakdown voltage is lower than +VCC, QEXT can be protected with a 12V zener diode connected from gate to source. Two PNP discrete transistors (Darlington-connected) can be used for QEXT—see Figure 2. Note that an additional capaci- tor is required for stability. Integrated Darlington transistors are not recommended because their internal base-emitter resistors cause excessive error. TRANSISTOR DISSIPATION Maximum power dissipation of QEXT depends on the power supply voltage and full-scale output current. Assuming that the load resistance is low, the power dissipated by QEXT is: PMAX = (+VCC) IFS (2) The transistor type and heat sinking must be chosen accord- ing to the maximum power dissipation to prevent overheat- ing. See Table II for general recommendations. PACKAGE TYPE ALLOWABLE POWER DISSIPATION TO-92 Lowest: Use minimum supply and at +25 °C. TO-237 Acceptable: Trade-off supply and temperature. TO-39 Good: Adequate for majority of designs. TO-220 Excellent: For prolonged maximum stress. TO-3 Use if hermetic package is required. TABLE II. External Transistor Package Type and Dissipation. INPUT VOLTAGE RANGE The internal op amp A1 can be damaged if its non-inverting input (an internal node) is pulled more than 0.5V below common (0V). This could occur if input pins 3, 4 or 5 were driven with an op amp whose output could swing negative under abnormal conditions. The voltage at the input of A1 is: VA1 = + + (3) This voltage should not be allowed to go more negative than –0.5V. If necessary, a clamp diode can be connected from the negative-going input to common to clamp the input voltage. COMMON (Ground) Careful attention should be directed toward proper con- nection of the common (grounds). All commons should be joined at one point as close to pin 2 of the XTR110 as possible. The exception is the IOUT return. It can be returned to any point where it will not modulate the common at pin 2. VOLTAGE REFERENCE The reference voltage is accurately regulated at pin 12 (VREF SENSE). To preserve accuracy, any load including pin (V REF IN) 16 (V IN1) 4 (V IN2) 2 FIGURE 2. Q EXT Using PNP Transistors. XTR110 47nF R L I OUT 1 13 14 +V CC 16 2 2N2907 etc. TIP30B etc. 0.047µF Common 3 should be connected to this point. The circuit in Figure 3 shows adjustment of the voltage reference. The current drive capability of the XTR110’s internal refer- ence is 10mA. This can be extended if desired by adding an external NPN transistor shown in Figure 4. OFFSET (ZERO) ADJUSTMENT The offset current can be adjusted by using the potentiom- eter, R1, shown in Figure 5. Set the input voltage to zero and then adjust R1 to give 4mA at the output. For spans starting FIGURE 4. Increasing Reference Current Drive. XTR110 15 12 +V CC 16 2 Sense Force For 100mA with V CC up to 40V use 2N3055 for Q REF. Q REF +10V REF FIGURE 3. Optional Adjustment of Reference Voltage. XTR110 V REF Adjust 15 12 11 V REF Sense V REF Force +V CC 16 Common 2 V REF R 20k Ω R S (1) Adjust Range ±5% Optimum NOTE: (1) R S gives higher resolution with reduced range, set R S = 0Ω for larger range. |
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