© 2002 Fairchild Semiconductor Corporation

DS500646

www.fairchildsemi.com

September 2001

Revised February 2002

74ALVC162835

Low Voltage 18-Bit Universal Bus Driver

with 3.6V Tolerant Inputs/Outputs

and 26

Ω Series Resistors in Outputs

General Description

The ALVC162835 low voltage 18-bit universal bus driver

combines D-type latches and D-type flip-flops to allow data

flow in transparent, latched and clocked modes.

Data flow is controlled by output-enable (OE), latch-enable

(LE), and clock (CLK) inputs. The device operates in

Transparent Mode when LE is held HIGH. The device

operates in clocked mode when LE is LOW and CLK is tog-

a Positive Edge Transition of the Clock. When OE is LOW,

the output data is enabled. When OE is HIGH the output

port is in a high impedance state.

The ALVC162835 is designed with 26

Ω series resistors in

the outputs. This design reduces noise in applications such

as memory address drivers, clock drivers, and bus trans-

ceivers/transmitters.

The 74ALVC162835 is designed for low voltage (1.65V to

The 74ALVC162835 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing low CMOS power dissipation.

Features

s Compatible with PC100 DIMM module specifications

s 3.6V tolerant inputs and outputs

s 26

Ω series resistors in outputs

s Power-off high impedance inputs and outputs

s Supports live insertion/withdrawal (Note 1)

s Latchup conforms to JEDEC JED78

s ESD performance:

Human body model

> 2000V

Machine model

>200V

Note 1: To ensure the high impedance state during power up or power

value of the resistor is determined by the current sourcing capability of the

driver.

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Order Number

Package

Number

Package Description

74ALVC162835T

MTD56

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide