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AD608AR Datasheet(PDF) 9 Page - Analog Devices

Part # AD608AR
Description  Low Power Mixer/Limiter/RSSI 3 V Receiver IF Subsystem
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD608AR Datasheet(HTML) 9 Page - Analog Devices

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AD608
Rev. C | Page 9 of 16
THEORY OF OPERATION
The AD608 consists of a mixer followed by a logarithmic IF
strip with RSSI and hard-limited outputs (see Figure 22).
MIXER
The mixer is a doubly balanced, modified gilbert-cell mixer. Its
maximum input level for linear operation is either ±56.2 mV,
regardless of the impedance across the mixer inputs, or −15 dBm
for a 50 Ω input termination. The input impedance of the mixer
can be modeled as a simple parallel RC network; the resistance
and capacitance values vs. frequency are listed in Table 5. The
bandwidth from the RF input to the IF output at the MXOP pin
is −1 dB at 30 MHz and then rapidly decreases as frequency
increases (see Figure 4).
MIXER GAIN
The conversion gain of the mixer is the product of its trans-
conductance and the impedance seen at Pin MXOP. For a 330 Ω
parallel-terminated filter at 10.7 MHz, the load impedance is
165 Ω, the gain is 24 dB, and the output is 15.85 × 56.2 mV (or
±891 mV) centered on the midpoint of the supply voltage. For
other load impedances, the expression for the gain in decibels is
GdB = 20 log10(0.0961 RL)
where:
GdB is the gain in decibels.
RL is the load impedance at Pin MXOP.
The gain of the mixer can be increased or decreased by changing
RL. The limitations on the gain are the ±6 mA maximum output
current at MXOP and the maximum allowable voltage swing at
Pin MXOP, which is ±1.0 V for a 3 V supply or 5 V supply.
24dB MIXER GAIN
110dB LIMITER GAIN
90dB RSSI
BIAS
MXOP
MIXER
BPF
DRIVER
VMID
LO
PREAMP
AD608
RFHI
RFLO
IF INPUT
–75dBm TO
+15dBm2
IFHI
IFLO
LMOP
VPS2
RSSI
FDBK
COM3
FINAL
LIMITER
100nF
10nF
330
±50µA
330
MIDSUPPLY
IF BIAS
LIMITER
OUTPUT
400mV p-p
PRUP
RF INPUT
–95dBm TO
–15dBm1
VPS1 COM1
COM2
LOHI
RSSI OUTPUT
20mV/dB
0.2V TO 1.8V
3dB NOMINAL
INSERTION LOSS
2.7V TO 5.5V
5-STAGE IF AMPLIFIER
(16dB PER STAGE)
7 FULL-WAVE
RECTIFIER CELLS
2.7V TO
5.5V
LO INPUT
–16dBm
CMOS LOGIC
INPUT
±6mA MAX OUTPUT
(±890mV INTO 165Ω)
100
18nF
1–15dBm = ±56mV MAXIMUM FOR LINEAR OPERATION.
239.76µV RMS TO 397.6mV RMS FOR ±1dB RSSI ACCURACY.
2MHz
LPF
10.7MHz
BAND-PASS
FILTER
5
6
1
2
3
4
16
8
7
10
13
9
15
14
12
11
+
Figure 22. Functional Block Diagram
Table 5. Mixer Input Impedance vs. Frequency
Frequency (MHz)
Resistance (Ω)
Capacitance (pF)
45
2800
3.1
70
2600
3.1
100
1900
3.0
200
1200
3.1
300
760
3.2
400
520
3.4
500
330
3.6


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