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PCF85063ATL Datasheet(PDF) 4 Page - NXP Semiconductors

Part # PCF85063ATL
Description  Tiny Real-Time Clock/calendar with alarm function and I2C-bus
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

PCF85063ATL Datasheet(HTML) 4 Page - NXP Semiconductors

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PCF85063ATL
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 15 April 2013
4 of 54
NXP Semiconductors
PCF85063ATL
Tiny Real-Time Clock/calendar with alarm function and I2C-bus
8.
Functional description
The PCF85063ATL contains 18 8-bit registers with an auto-incrementing register address,
an on-chip 32.768 kHz oscillator with integrated capacitors, a frequency divider which
provides the source clock for the Real-Time Clock (RTC) and calender, and an I2C-bus
interface with a maximum data rate of 400 kbit/s.
The built-in address register will increment automatically after each read or write of a data
byte up to the register 11h. After register 11h, the auto-incrementing will wrap around to
address 00h (see Figure 3).
All registers (see Table 5) are designed as addressable 8-bit parallel registers although
not all bits are implemented. The first two registers (memory address 00h and 01h) are
used as control and status register. The register at address 02h is an offset register
allowing the fine-tuning of the clock; and at 03h is a free RAM byte. The addresses 04h
through 0Ah are used as counters for the clock function (seconds up to years counters).
Address locations 0Bh through 0Fh contain alarm registers which define the conditions for
an alarm. The registers at 10h and 11h are for the timer function.
The Seconds, Minutes, Hours, Days, Months, and Years as well as the corresponding
alarm registers are all coded in Binary Coded Decimal (BCD) format. When one of the
RTC registers is written or read, the contents of all time counters are frozen. Therefore,
faulty writing or reading of the clock and calendar during a carry condition is prevented.
For details on maximum access time, see Section 8.4 on page 22.
Fig 3.
Handling address registers
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