AD9508BCPZ-REEL7 datasheet(9/40 Pages) AD

Part #	AD9508BCPZ-REEL7

Description	1.65 GHz Clock Fanout Buffer with Output Dividers and Delay Adjust

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Data Sheet

AD9508

Rev. A | Page 9 of 40

CLOCK OUTPUT ADDITIVE TIME JITTER

Table 9.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LVDS OUTPUT ADDITIVE TIME JITTER

CLK = 622.08 MHz, Outputs = 622.08 MHz

41

fs rms

BW = 12 kHz to 20 MHz

70

fs rms

BW = 20 kHz to 80 MHz

69

fs rms

BW = 50 kHz to 80 MHz

CLK = 622.08 MHz, Outputs = 155.52 MHz

93

fs rms

BW = 12 kHz to 20 MHz

144

fs rms

BW = 20 kHz to 80 MHz

142

fs rms

BW = 50 kHz to 80 MHz

CLK = 125 MHz, Outputs = 125 MHz

105

fs rms

BW = 12 kHz to 20 MHz

209

fs rms

BW = 20 kHz to 80 MHz

206

fs rms

BW = 50 kHz to 80 MHz

CLK = 400 MHz, Outputs = 50 MHz

184

fs rms

BW = 12 kHz to 20 MHz

HSTL OUTPUT ADDITIVE TIME JITTER

CLK = 622.08 MHz, Outputs = 622.08 MHz

41

fs rms

BW = 12 kHz to 20 MHz

56

fs rms

BW = 100 Hz to 20 MHz

72

fs rms

BW = 20 kHz to 80 MHz

70

fs rms

BW = 50 kHz to 80 MHz

CLK = 622.08 MHz, Outputs = 155.52 MHz

76

fs rms

BW = 12 kHz to 20 MHz

87

fs rms

BW = 100 Hz to 20 MHz

158

fs rms

BW = 20 kHz to 80 MHz

156

fs rms

BW = 50 kHz to 80 MHz

CMOS OUTPUT ADDITIVE TIME JITTER

CLK = 100 MHz, Outputs = 100 MHz

91

fs rms

BW = 12 kHz to 20 MHz

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