SPRAAW9 datasheet(4/214 Pages) TI

Part #	SPRAAW9

Description	TMS320C6474 Multicore Digital Signal Processor

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Manufacturer	TI [Texas Instruments]

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TMS320C6474

SPRS552H

– OCTOBER 2008 – REVISED APRIL 2011

www.ti.com

The device includes two Serial RapidIO® (SRIO) with link rates of 1.25 Gbps, 2.5 Gbps or 3.125 Gbps.

This high-bandwidth peripheral is used for point-to-point inter-device communication and may connect the

C6474 device to other DSPs, ASICs, or switches on the same board or across the backplane. This

dramatically improves system performance and reduces system cost for applications that include multiple

DSPs on a board such as video and telecom infrastructures and medical/imaging. The SRIO also provides

alarm, interrupt, and messaging events.

The device includes the SerDes-based antenna interface (AIF) capable of up to 3.072 Gbps operation per

link. The AIF comprises six high-speed serial links, compliant to OBSAI RP3 and CPRI standards. The

antenna interface is used to connect the backplane for antenna data transmission and reception. Each link

of the AIF includes a differential receive and transmit signal pair.

1.2.3

Accelerators

The device has two high-performance embedded coprocessors [enhanced Viterbi Decoder Coprocessor

(VCP2) and enhanced turbo decoder coprocessor (TCP2)] that significantly speed up channel-decoding

operations on-chip. The VCP2 operating at CPU clock divided-by-3 can decode over 694 7.95-Kbps

adaptive multi-rate (AMR) [K=9, R=1/3] voice channels. The VCP2 supports constraint lengths K = 5, 6, 7,

8, and 9, rates R = 3/4, 1/2, 1/3, and 1/5, and flexible polynomials, while generating hard decisions or soft

decisions. The TCP2 operating at CPU clock divided-by-3 can decode up to fifty 384-Kbps or eight

2-Mbps turbo encoded channels (assuming 6 iterations). The TCP2 implements the max*log-map

algorithm and is designed to support all polynomials and rates required by third-generation partnership

projects (3 GPP and 3 GPP2), with fully programmable frame length and turbo interleaver. Decoding

parameters such as the number of iterations and stopping criteria are also programmable.

Communications between the VCP2/TCP2 and the CPU are carried out through the EDMA3 controller.

4

Features

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