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T8535B Datasheet(PDF) 6 Page - Agere Systems |
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T8535B Datasheet(HTML) 6 Page - Agere Systems |
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6 / 50 page  6 Agere Systems Inc. Preliminary Data Sheet September 2001 T8535B/T8536B Quad Programmable Codec Pin Information (continued) Table 2. Pin Assignments, 44-Pin PLCC, Common Functions Pin Name Type Name/Description 1DO O Serial Data Output. This is a 3-state output. 2DI I Serial Data Input. 3DCLK I Serial Data Clock Input. 4CS I Chip Select Input. This lead determines the interval that the serial interface is active. 5INTS I Serial Interface Select. Leaving this lead open places the serial interface in the nor- mal mode; grounding it places the interface into the byte-by-byte mode. This lead has an internal pull-up. 6FILTV PWR Frequency Synthesizer Power (5 V). This pin must be tied to VDD. 7PVCOIN — Internal Test Point. Do not connect to this lead. 8PVCO — Internal Test Point. Do not connect to this lead. 9PLLT — Synthesizer Test Point. Do not connect to this lead. 10 SGND GND Synthesizer Ground. Connect to digital ground. A common AGND, DGND, SGND plane is highly recommended. 16, 29, 38, 44 DGND GND Digital Ground. Logic ground and return for logic power supply. A common AGND, DGND, SGND plane is highly recommended. 17, 28, 35, 42 VDD PWR Digital Power Supply (5 V). 36 FS I PCM Frame Strobe Input. This 8 kHz clock must be derived from the same source as BCLK. 37 BCLK I PCM Bit Clock Input. This lead is used to develop internal clocks for certain clock rates. 39 DX O PCM Transmit Data Output. This is a 3-state output. 40 DR I PCM Receive Data Input. 41 RST I Power-On Reset. A low causes a reset of the entire chip. This pin may be con- nected to DGND with a 0.1 µF capacitor for a power-on reset function, or it may be driven by external logic. This lead has an internal pull-up. 43 NC — No Connect. This pin may be used as a tie point. |
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