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T8533 Datasheet(PDF) 4 Page - Agere Systems |
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T8533 Datasheet(HTML) 4 Page - Agere Systems |
4 / 48 page Preliminary Data Sheet July 2001 Signal Processor T8533/34 Quad Programmable Line Card 4 Agere Systems Inc. Functional Description (continued) The SLIC interface is designed to be flexible and con- venient to use with a variety of SLIC circuits. With an appropriate choice of SLIC, no external components are required in the interface, with the exception of a dc blocking capacitor in the transmit direction. In some cases, dc blocking capacitors in the receive direction may be necessary as well, since the device operates from a single 5 V supply. The PCM bus interface is flexible in that it allows, inde- pendently, the transmit and receive data for any chan- nel to be placed in any time slot. The bus can be operated at a maximum of a 16.384 Mbits/s rate to accommodate a maximum of 256 time slots. Separate pins are provided for each direction of transmission to allow 4-wire bus operation. The frame strobe signal is an 8 kHz signal that defines the beginning of the frame structure. The interface will count 8 bits per time slot and insert or read the data for each channel as pro- grammed. Lower speeds of the PCM bus are allowed. The PCM clock must be synchronous with the master clock for the device (if present) and with the frame strobe signal. The microprocessor control interface is a serial inter- face that uses the classic chip select type of operation. The interface controls the device by writing or reading various internal addresses. The command set com- prises simple read and write operations, with the address determining the effect. All the memory loca- tions, including the per-chip functions, are organized by channel, allowing a straightforward migration path to architectures other than quad. There are several test modes included to facilitate confirmation of correct operation. In the signal path, both an analog and four digital loopback tests are avail- able, while in the microprocessor interface, there is a write/read test mode that tests the operation of the memory. Use of external test access switches allows a complete test of the signal path through the line card so that correct operation of various operational modes can be verified. |
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