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T8533 Datasheet(PDF) 3 Page - Agere Systems |
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T8533 Datasheet(HTML) 3 Page - Agere Systems |
3 / 48 page Preliminary Data Sheet July 2001 Signal Processor T8533/34 Quad Programmable Line Card Agere Systems Inc. 3 Functional Description Refer to Figure 1 for the following discussion. (It should be noted that much of the processing is performed in a dig- ital processor; thus, the actual data flow may be different than this functional, analog analogy based diagram shows.) 5-7172.ar5(F) Figure 1. Functional Block Diagram, Each Section RST MCLK SLIC TO/FROM ANALOG GAIN A/D CONVERTER ANALOG BUFFER D/A CONVERTER TERMINATION IMPEDANCE ECHO CancellER DIGITAL GAIN (GAIN TRANSFER) µ-LAW PER CHANNEL COMMON PCM BUS INTERFACE DX DR TO/FROM PCM BUS POWER AND GROUND 18 FS BCLK SLIC CONTROL LATCHES MICROPROCESSOR CONTROL CONTROL AND DATA SIGNALS 4 SERIAL CONTROL INTERFACE PER CHANNEL COMMON 0 TO 6 FREQUENCY SYNTHESIZER 3 FACTORY TEST OR CONVERSION A-LAW DIGITAL GAIN (GAIN TRANSFER) – VFXINn VFROPn VFRONn This device performs virtually all the signal processing functions associated with a central office line termina- tion. Functionality includes line termination impedance synthesis, adaptive or fixed hybrid balance (echo can- celler), and level conversion both in the analog sense (transmit equalization), to accommodate various sub- scriber line interface circuits (SLICs), and in the digital sense, for adjustment of the levels on the PCM bus (gain transfer). In general, the termination impedance synthesis generates the equivalent of a circuit with the parallel combination of a capacitor and a resistor in series with a resistor or the parallel combination of a resistor and the series combination of a resistor and capacitor. These general forms of impedance charac- teristic will satisfy most of the requirements specified throughout the world. Programmable selection of either µ-law or A-law encoding further aids worldwide deploy- ment. In addition to the programmable features for impedance and coding, the device also contains an echo canceller that meets international requirements for network echo cancellers. This includes the ability to automatically disable the adaptation in the presence of 2100 Hz modem tones. All coefficients used in the fil- tering algorithms can be computed off-line in advance and downloaded to the device at the time of powerup. All signal processing is contained within the device, and there are only three interfaces of consequence to the system designer: the SLIC interface, the PCM inter- face, and the control interface. |
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