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T8533 Datasheet(PDF) 8 Page - Agere Systems

Part # T8533
Description  T8533/34 Quad Programmable Line Card Signal Processor
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Manufacturer  AGERE [Agere Systems]
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T8533 Datasheet(HTML) 8 Page - Agere Systems

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Preliminary Data Sheet
July 2001
Signal Processor
T8533/34 Quad Programmable Line Card
8
Agere Systems Inc.
Pin Information (continued)
Table 4. Pin Assignments, 68-Pin PLCC, Common Functions
Pin
Name
Type
Name/Description
1DO
O
Serial Data Output. This is a 3-state output.
2DI
I
Serial Data Input.
3
DCLK
I
Serial Data Clock Input.
4CS
I
Chip Select Input. This pin determines the interval that the serial interface is
active.
5INTS
I
Serial Interface Select. Leaving this pin open places the serial interface in
the normal mode; grounding it places the interface into the byte-by-byte
mode. This pin has an internal pull-up.
10
FILTV
PWR
Frequency Synthesizer Power (5 V). This pin must be tied to VDD.
11
PVCOIN
Internal Test Point. Do not connect to this pin.
12
PVCO
Internal Test Point. Do not connect to this pin.
13
PLLT
Internal Test Point. Do not connect to this pin.
14
SGND
GND
Synthesizer Ground. Connect to DGND. A common AGND, DGND, SGND
plane is highly recommended.
24, 45, 58, 68
DGND
GND
Digital Ground. Logic ground and return for logic power supply. A common
AGND, DGND, SGND plane is highly recommended.
28, 40, 55, 66
VDD
PWR
Digital Power Supply (5 V).
56
FS
I
PCM Frame Strobe Input. This 8 kHz clock must be derived from the same
source as BCLK. See the Clocking Considerations section.
57
BCLK
I
PCM Clock Input. This pin is used to develop internal clocks for certain clock
rates. See the Clocking Considerations section.
59
DX
O
PCM Bus Output Pin. This is a 3-state output.
60
DR
I
PCM Bus Input Pin.
65
RST
I
Power-On Reset. A low causes a reset of the entire chip. This pin may be
connected to DGND with a 0.1
µF capacitor for a power-on reset function, or
it may be driven by external logic. This pin has an internal pull-up.
67
MCLK
I
1.024 MHz Master Clock Input. Internal timing is derived from this clock
input for certain PCM bus rates. See the Clocking Considerations section.
When unused, this pin may be left open. This pin has an internal pull-up.


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