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T8531A Datasheet(PDF) 10 Page - Agere Systems

Part # T8531A
Description  T8531A/8532 Multichannel Programmable Codec Chip Set
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Manufacturer  AGERE [Agere Systems]
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10
Agere Systems Inc.
Preliminary Data Sheet
September 2001
Codec Chip Set
T8531A/T8532 Multichannel Programmable
Pin Information (continued)
Table 2. T8531A Pin Descriptions
Note: TI = TTL input, TO = TTL output; CI = CMOS input, CO = CMOS output; AI = analog input, AO = analog output; Iu indicates a pull-up
device is included on this lead.
Number
Name
Type
Name/Function
29
UPDI
TI
Control Data Interface Input. The microcontroller sends control register
address and data to the T8531A through this pin.
30
UPDO
TO
Control Data Interface Output. The microcontroller receives control regis-
ter contents from this pin. Inactive state is high impedance.
27
UPCK
TI
Control Data Interface Clock. Bit clock for the control interface. Speed is
limited to 4.096 MHz.
28
UPCS
TI
Control Interface Chip Select (Active-Low). This active-low input enables
the control interface.
43, 45,
36, 38
OSDX[3:0]
CI
Oversampled Transmit Data. Four channels of 1 Msamples/s
Σ-∆ transmit
data are received from the T8532 chips through each of these pins. The data
rate is 4.096 MHz.
42, 44,
35, 37
OSDR[3:0]
CO
Oversampled Receive Data. Four channels of 1 Msamples/s
Σ-∆ receive
data is transmitted to the T8532 chips on each of these pins. The data rate is
4.096 MHz.
39
OSCK
CO
4.096 MHz Clock. Clock for data transfer to/from T8532 chips.
40
OSFS
CO
Oversampling Sync. 8 kHz synchronization pulse for data transfer
to/from T8532 chips.
11
VDDA
Synthesizer VDD. Power supply for clock synthesizer block.
13
VSSA
Synthesizer Ground. Ground connection for the clock synthesizer block.
24
STSXB
TO
Backplane Drive Enable (Active-Low). Active when SDX is transmitting
valid data; high impedance otherwise. This pin provides an enable signal for
a backplane line driver.
20
SCK
TI
Master Clock Input. This is the bit clock used to shift data into and out of the
SDR and SDX pins. It is the input to the clock synthesizer and is used to
generate all internal clocks. Rate is 4.096 MHz.
17
SCKSEL
TIu
Master Clock Select Input. A logic low selects the 2.048 MHz SCK. A logic
high selects the 4.096 MHz SCK. An internal pull-up device is included, pro-
viding 4.096 MHz SCK operation with no external connections.
22
SDR
TI
Receive PCM Input. The data on this pin is shifted into the T8531A on the
falling edges of SCK. Data is only entered for valid time slots as defined in
the TSA registers.


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