Electronic Components Datasheet Search |
|
T8531A Datasheet(PDF) 8 Page - Agere Systems |
|
T8531A Datasheet(HTML) 8 Page - Agere Systems |
8 / 50 page 8 Agere Systems Inc. Preliminary Data Sheet September 2001 Codec Chip Set T8531A/T8532 Multichannel Programmable Pin Information (continued) Table 1. T8532 Pin Descriptions Note: TI = TTL input, TO = TTL output; CI = CMOS input, CO = CMOS output; AI = analog input, AO = analog output; Iu indicates a pull-up device is included on this lead, Id indicates a pull-down device is included on this lead. Number Name Type Name/Function 64, 8, 10, 18, 31, 39, 41, 49 VTX[7:0] AI Analog Input. Transmit signal voltage to be encoded. 1, 7, 11, 17, 32, 38, 42, 48 VRTX[7:0] AI Transmit Reference Voltage. 2.4 V reference. Each pin must have a sep- arate supply associated with the corresponding VTX pin. 2, 6, 12, 16, 33, 37, 43, 47 VRP[7:0] AO Noninverting Receive Output. This pin can drive high-impedance loads either differentially or single ended. It is the complement of the VRN output. 3, 5, 13, 15, 34, 36, 44, 46 VRN[7:0] AO Inverting Receive Output. This pin can drive high-impedance loads either differentially or single ended. It is the complement of the VRP output. 9, 19, 27, 30, 40, 50, 63 VDDA — 5 V Analog Power Supply. Power supply decoupling capacitor (0.1 µF) should be connected from each VDDA pin to analog ground. Capacitors should be located as close as possible to the device pins. 4, 14, 21, 35, 45 VSSA — Analog Ground. 51 VDDD — 5 V Digital Power Supply. Decouple with a 0.1 µF capacitor to digital ground. 62 VSSD — Digital Ground. 60, 59 OSDX[1:0] CO Oversampled Transmit Data. Four channels of 1.024 MHz Σ-∆ transmit data is transmitted to the T8531A through each of these pins. The data rate is 4.096 MHz. 61, 58 OSDR[1:0] CI Oversampled Receive Data. Four channels of 1.024 MHz Σ-∆ receive data is received from the T8531A on each of these pins. The data rate is 4.096 MHz. 57 OSCK CI Interface Clock. The 4.096 MHz clock that enters this pin from the T8531A serves as the bit clock for all the oversampled data transmission between this chip and the T8531A This is the master clock input for the T8532. 56 OSFS CI Interface Frame Sync. This signal serves as the frame sync for the over- sampled data interface between the T8532 and the T8531A 54 CDI CI Control Data Interface Input. The T8531A sends control register address and data to the T8532 through this pin. One address byte and one data byte are accepted each time CCS is toggled. 52 CDO CO Control Data Interface Output. Control register contents are clocked out through this pin. 53 CCS CI Control Interface Chip Select (Active-Low). This active-low input enables the control interface. 55 RSTB TIu Reset (Active-Low). This input must be pulled high for normal operation. When pulled momentarily low (at least 1 µs) while OSCK is active, all pro- grammable registers in the device are reset to the states specified under powerup initialization. This pin has an internal pull-up resistor. 20, 22—26, 28, 29 NC — No Connect. No connection to chip. These pins can be used as logic level tie points. |
Similar Part No. - T8531A |
|
Similar Description - T8531A |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |