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T8502 Datasheet(PDF) 2 Page - Agere Systems |
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T8502 Datasheet(HTML) 2 Page - Agere Systems |
2 / 16 page 2 2 Lucent Technologies Inc. Data Sheet July 1998 T8502 and T8503 Dual PCM Codecs with Filters Functional Description Two channels of PCM data input and output are passed through only two ports, DX and DR, so some type of time-slot assignment is necessary. The scheme used here is to utilize a fixed-data rate mode of 32 or 64 time slots corresponding to master clock frequencies of either 2.048 MHz or 4.096 MHz, respectively. Each device has four frame sync (FSX and FSR) inputs, one pair for each channel. During a single 125 µs frame, each frame sync input is supplied a single pulse. The timing of the respective frame sync pulse indicates the beginning of the time slot during which the data for that channel is clocked in or out of the device. FSX and FSR must be high for a minimum of one master clock cycle. They can be operated independently, or they can be tied together for coincident transmit and receive data transfer. During a frame, channel 0 and 1 transmit frame sync pulses must be separated from each other by one or more time slots. Likewise, channel 0 and 1 receive frame sync pulses must be separated from each other by one or more time slots. Both transmit and receive frame strobes must be derived from master clock, but they do not need to be byte aligned. A channel is placed in standby mode by removing both FSX and FSR for 500 µs. Note, if any one of those pulses (per channel) is removed, operation is indeter- minate. Standby mode reduces overall device power consumption by turning off nonessential circuitry. Criti- cal circuits that ensure a fast, quiet powerup are kept active. Master clock need not be active when both channels are in standby mode. The frequency of the master clock must be either 2.048 MHz or 4.096 MHz. Internal circuitry determines the master clock frequency during the powerup reset interval. The analog input section in Figure 2 includes an on- chip op amp that is used in conjunction with external, user-supplied resistors to vary encoder passband gain. The feedback resistance (RF) should range from 10 k Ω to 200 k Ω, and capacitance from GSX to ground should be kept to less than 50 pF. The input signal at VFXIN should be ac coupled. For best performance, the maxi- mum gain of this op amp should be limited to 20 dB or less. Gain in the receive path is selectable via the GS pins as either 0 dB or –3.5 dB. 5-3786.a Figure 2. Typical Analog Input Section Pin Information 5-3788.b Figure 3. Pin Diagram VFXIN TO CODEC FILTERS 2.4 V GAIN = RF RI GSX RF CI RI – + VFXIN0 GSX0 GS0 FSR0 MCLK GNDD DR DX VFXIN1 GSX1 ASEL FSR1 FSX1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 FSX0 T-8502 T-8503 VFRO0 GNDA0 VDD VFRO1 GNDA1 GS1 |
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