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T8207 Datasheet(PDF) 8 Page - Agere Systems

Part # T8207
Description  ATM Interconnect
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Manufacturer  AGERE [Agere Systems]
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8
Agere Systems Inc.
Advance Data Sheet
September 2001
ATM Interconnect
CelXpres T8207
1
Product Overview (continued)
1.3
Description
The
CelXpres T8207 device integrates all of the required functionality to transport ATM cells across a backplane
architecture with high-speed cell traffic exceeding 1.5 Gbits/s to a maximum of 32 destinations. The management
of multiple service categories and monitoring of performance on ATM and PHY interfaces is incorporated in the
device’s functionality. Traffic delivery to multi-PHYs (MPHYs) is managed through the UTOPIA interface.
The T8207 device meets the ATM Forum’s universal test and operations PHY interface for ATM (UTOPIA) Level 1,
Version 2.01 and Level 2, Version 1.0 specifications for cell-level handshake and MPHY data path operation with
rates up to 353 Mbits/s. The T8207 supports the required MPHY operation as described in Sections 4.1 and 4.2 of
the ATM Forum’s Level 2 specification. The T8207 supports MPHY operation with one transmit cell available
(TxCLAV) signal and one receive cell available (RxCLAV) signal for up to 16 PHY ports for an 8-bit UTOPIA 2 inter-
face configuration. With two transmit cells available/enable (TxCLAV/enb*) pairs of signals and receive cells avail-
able/enable (RxCLAV/enb*) pairs of signals, 32 MPHYs can be supported. In addition to the required UTOPIA
signals, the optional transmit parity (TxPRTY) and receive parity (RxPRTY) signals are provided.
The T8207 may be configured as an ATM or PHY level device providing cell routing between UTOPIA and a 32-bit
wide cell bus. In addition to the 32 data signals, the bus has the following signals:
s
Read clock
s
Write clock
s
Frame sync
s
Acknowledge
ATM cells arriving from the UTOPIA interface may get VPI and VCI translation and routing information from a look-
up table in external SRAM. An external synchronous dynamic random access memory (SDRAM) is used to extend
the buffering for ATM cells destined for the UTOPIA interface. This external SDRAM may be partitioned into four or
less independently sized queues per PHY for a configuration of 16 MPHYs and two queues per PHY or a program-
mable number of queues per PHY for a configuration of 32 MPHYs. The number of cells per queue per PHY is pro-
grammable. The four queues may be used to implement quality of service (QoS) using different priorities for each
queue.
The
CelXpres T8207 provides a shared UTOPIA mode, which allows two devices on different cell buses to share
the same UTOPIA bus in ATM mode. Using a glueless interface, the two T8207 devices resolve queue priorities
and arbitrate the use of the UTOPIA bus. This shared mode can be used to provide redundancy or increase
UTOPIA traffic capacity by supporting traffic from multiple cell buses.
The
CelXpres T8207 supports the transport of control and loopback cells with an external microprocessor. Control
or loopback cells may be sent or received through the microprocessor interface. The 8-bit microprocessor interface
may be configured to be
Motorola or Intel compatible and is used to configure and monitor the device.


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