Advance Data Sheet, Rev. 1

October 2001

Recovery for 2.488 Gbits/s Applications

R485-Type Lightwave Receiver with Clock

Agere Systems Inc.

7

PWB Layout Guidelines

s

The data and clock outputs are designed to drive 50

Ω loads.

s

Clock and data output traces must be controlled-impedance lines and the termination impedance must match

the line impedance. Avoid 90

° bends in the traces. Paired lines (i.e., DATA and DATA) must be equal in length.

s

Data and clock output lines should be as short and straight as possible and should be shielded from noise

sources to prevent noise from feeding back into the receiver.

s

Use high-quality multilayer printed-wiring boards. A ground plane should occupy the area directly beneath the

receiver.

1-934(F)xxx

Note 1: Data and clock outputs must be ac-coupled on customer board. Use a 0.1

µF chip capacitor with a low ESR. For optimum receiver per-

formance, all four outputs must be terminated in equivalent loads, even if some of the outputs are not being used.

Note 2: The 0.1

the appropriate power supply leads and should provide a low inductance path to the ground plane.

Figure 4. Biasing and Interfacing to the R485-Type 2.5 Gbits/s Receiver

8, 22

5

6

10

11

CLOCK

CLOCK

DATA

DATA

50

Ω TRANSMISSION

4, 7, 9, 12,

2.2

µF

15

µF

+5 V

0.1

µF

50

Ω

+

14—17, 19, 20

LINE (4X)

1

µH

0.1

µF

NOTE 2

NOTE 1

LOS (FLAG)

3

0.1

µF

NIC

1

0.1

µF