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Lucent Technologies Inc.

Advance Data Sheet

DNC5X3125

March 2000

Gigabit Ethernet Transceiver Macrocell

Powerup Sequence

An appropriate powerup reset (PUR) standard cell must be placed in the ASIC to hold the transceiver in reset until

full power is supplied to the macrocell. REFCLK must be active at the time the PUR output goes low and must stay

active while powered up, unless in Reset.

When PUR and signals RESET, BYPPLL, and LPWR are all low, the following start-up sequence occurs:

1. 0 µs—32 µs, the analog PLL is held at minimum frequency to allow dc bias to settle.

2. 32 µs—262 µs, the analog PLL has locked in and receiver analog circuits start to lock in.

3. 262 µs—326 µs, the receiver analog circuits are locked; receiver starts to lock onto incoming data.

4. After 358 µs, receiver is locked onto incoming data and can be viewed at the parallel output ports. The comma

detect circuit is enabled at this point allowing byte alignment if ENCDET = 1.

If LCKREFN goes low after the 358 µs, the receiver will sit idle. When LCKREFN goes high, the receiver will be

locked onto data after 2 µs.

Macrocell Reset

The RESET input to the macrocell is an active-high. When activated with a pulse duration of 1 µs, the RESET sig-

nal globally resets the macrocell and the following is performed:

1. The single analog PLL is forced to operate at the minimum frequency possible for its VCO. The PLL will not be

locked in this condition.

2. The high-speed serial output HDOUTP is forced to a PECL logic 0, HDOUTN to logic 1.

3. The deserializer clocks are reset, input data at HDINP, HDINN is ignored and the RX[9:0] signals remain in their

previous state.

4. The phase interpolation/selection circuits are deactivated and the selected phase is reset.

5. The receiver digital low-pass filter in the DPLL is reset. Normally, a reset is not necessary for correct operation,

although a reset can aid rapid lock-in of the internal PLL circuitry.

Sleep Mode

The DNC5X3125 has a sleep mode that is activated by enabling LPWR. In this mode, a divided-down version of

the REFCLK is used to refresh the dynamic circuits within the transceiver. The PLL is powered down in this mode

also. LCKREFN can also be activated to reduce the power even further. Note that complete power down for IDDQ

testing is not supported due to the dynamic logic used in the high-speed sections of the transceiver. The lock-in

sequence timing is needed when coming out of sleep mode.