Lucent Technologies Inc.

5

Data Sheet

January 1999

BDG1A, BDP1A, BDGLA, BPNGA, BPNPA, and BPPGA

Quad Differential Drivers

Timing Characteristics

Table 4. Timing Characteristics (See Figures 2 and 3.)

Propagation delay test circuit connected to output (see Figure 6).

± 0.5 V.

† CL = 5 pF. Capacitor is connected from each output to ground.

Parameter

Symbol

Min

Typ

Max

Unit

Propagation Delay:

0.8

1.2

2.0

ns

0.8

1.2

2.0

ns

Capacitive Delay

—

0.02

0.03

ns/pF

Disable Time (either E1 or E2):

High-to-high Impedance

4

8

12

ns

Low-to-high Impedance

4

8

12

ns

Enable Time (either E1 or E2):

High Impedance to High

4

8

12

ns

High Impedance to Low

4

8

12

ns

—0.1

0.3

ns

—0.2

0.5

ns

Difference Between Drivers

——

0.3

ns

Rise Time (20%—80%)

—0.7

2

ns

Fall Time (80%—20%)

—0.7

2

ns