4

Agere Systems Inc.

Data Sheet

April 2001

BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A

Quad Differential Receivers

Timing Characteristics

Table 4. Timing Characteristics (See Figure 4 and Figure 5.)

Propagation delay test circuit connected to output is shown in Figure 6.

± 0.5 V.

12-3462(F)

Note: This graph is included as an aid to the system designers. Total circuit delay varies with load capacitance. The total delay is the sum of the

delay due to the external capacitance and the intrinsic delay of the device.

Figure 3. Typical Extrinsic Propagation Delay vs. Load Capacitance at 25 °C

Parameter

Symbol

Min

Typ

Max

Unit

Propagation Delay:

Input to Output High

1.5

2.5

4.0

ns

Input to Output Low

1.5

2.5

4.0

ns

High-to-high Impedance

—5

12

ns

Low-to-high Impedance

—5

12

ns

Pulse Width Distortion, ltpHL

− tpLHI:

tskew1

—

—

0.7

ns

tskew1

—

—

4.0

ns

Output Waveform Skews:

∆tskew1p-p

—

0.8

1.4

ns

∆tskew1p-p

—

—

1.5

ns

Same Part Skew

∆tskew

—

—

0.3

ns

Enable Time:

High Impedance to High

—8

12

ns

High Impedance to Low

—8

12

ns

Rise Time (20%—80%)

——

3.0

ns

Fall Time (80%—20%)

——

3.0

ns

25

50

75

100

125

150

0

2

1

3

7

175

200

0

4

5

6