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ACT-F512K8N-090F6Q Datasheet(PDF) 7 Page - Aeroflex Circuit Technology |
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ACT-F512K8N-090F6Q Datasheet(HTML) 7 Page - Aeroflex Circuit Technology |
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7 / 21 page  Aeroflex Circuit Technology SCD1668 REV A 4/28/98 Plainview NY (516) 694-6700 7 its control register architecture, alteration of the memory content only occurs after successful completion of spe- cific multi-bus cycle command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from Vcc power-up and power-down transitions or system noise. LOW Vcc WRITE INHIBIT To avoid initiation of a write cycle during Vcc power-up and power-down, a write cycle is locked out for VCC less than 3.2V (typically 3.7V). If VCC < VLKO, the command register is disabled and all internal program/erase cir- cuits are disabled. Under this condition the device will reset to read mode. Subsequent writes will be ignored until the Vcc level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when Vcc is above 3.2V. WRITE PULSE GLITCH PROTECTION Noise pulses of less than 5ns (typical) on OE, CE or WE will not initiate a write cycle. LOGICAL INHIBIT Writing is inhibited by holding anyone of OE = VIL, CE = VIH or WE = VIH. To initiate a write cycle CE and WE must be logical zero while OE is a logical one. POWER-UP WRITE INHIBIT Power-up of the device with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE. The internal state machine is automatically reset to the read mode on power-up. Write Operation Status D7 DATA POLLING The ACT-F512K8 features Data Polling as a method to indicate to the host that the internal algorithms are in progress or completed. During the program algorithm, an attempt to read the device will produce compliment data of the data last written to D7. During the erase algorithm, an attempt to read the device will produce a "0" at the D7 Output. Upon completion of the erase algorithm an attempt to read the device will produce a "1" at the D7 Output. For chip Erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six write pulse sequence. For sector erase, the Data Polling is valid after the last rising edge of the sector erase WE pulse. Data polling must be performed at a sector address within any of the sectors being erased and not a protected sector. Otherwise, the status may not be valid. Once the algo- rithm operation is close to being completed, data pins (D7) change asynchronously while the output enable (OE) is asserted low. This means that the device is driv- ing status information on D7 at one instance of time and then that byte's valid data at the next instant of time. Depending on when the system samples the D7 Output, it may read the status or valid data. Even if the device has completed internal algorithm operation and D7 has a valid data, the data outputs on D0 - D6 may be still invalid. The valid data on D0- D7 will be read on the suc- cessive read attempts. The Data Polling feature is only active during the programming algorithm, erase algo- rithm, or sector erase time-out. See Figures 6 and 10 for the Data Polling specifications. D6 TOGGLE BIT The ACT–F512K8 also features the "Toggle Bit" as a method to indicate to the host system that algorithms are in progress or completed. During a program or erase algorithm cycle, successive attempts to read data from the device will result in D6 toggling between one and zero. Once the program or erase algorithm cycle is completed, D6 Will stop toggling and valid data will be read on successive attempts. Dur- ing programming the Toggle Bit is valid after the rising edge of the fourth WE pulse in the four write pulse sequence. For chip erase the Toggle Bit is valid after the rising edge of the sixth WE pulse in the six write pulse sequence. For Sector erase, the Toggle Bit is valid after the last rising edge of the sector erase WE pulse. The Toggle Bit is active during the sector time out. See Figure 1 and 5. D5 EXCEEDED TIMING LIMITS D5 will indicate if the program or erase time has exceeded the specified limits. Under these conditions D5 will produce a "1". The Program or erase cycle was not successfully completed. Data Polling is the only operation function of the device under this condition. The CE circuit will partially power down the device under these conditions by approximately 2 mA. The OE and WE pins will control the output disable functions as shown in Table 1. To reset the device, write the reset command sequence to the device. This allows the sys- tem to continue to use the other active sectors in the device. D3 SECTOR ERASE TIMER After the completion of the initial sector erase command sequence the sector erase time-out will begin. D3 will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase com- mand sequence. |
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