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ACT-D1M32T-100F14T Datasheet(PDF) 5 Page - Aeroflex Circuit Technology |
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ACT-D1M32T-100F14T Datasheet(HTML) 5 Page - Aeroflex Circuit Technology |
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5 / 9 page  Aeroflex Circuit Technology SCD1661B REV A 1/16/97 Plainview NY (516) 694-6700 5 AC Characteristics – Write/Erase/Program Operations, CE Controlled (TA = -55 °C to +125°C, VCC = +4.5V to + 5.5V(5V Operation), or +3.0V to +3.6V(3.3V Operation), Unless otherwise specified) Parameter Symbol JEDEC Standard +3.3V VCC (2) Typical +4.5V to +5.5V VCC Units 120nS Min Max 80nS Min Max 100nS Min Max 120nS Min Max Write Cycle Time tAVAV 120 80 100 120 nS RP High Recovery to CE Low tPHEL 1.5 .45 .45 .45 µS WE Setup to CE Going Low tWLEL 0 0 0 0 nS Boot Block Unlock Setup to CE Going High (1) tPHHEH 200 100 100 100 nS VPP Setup to CE Going High (1) tVPEH 200 100 100 100 nS Address Setup to CE Going High tAVEH 90 60 60 60 nS Data Setup to CE Going High tDVEH 70 60 60 60 nS CE Pulse Width tELEH 90 60 60 60 nS Data Hold Time from CE High tEHDX 0 0 0 0 nS Address Hold Time from CE High tEHAX 0 0 0 0 nS WE Hold Time from CE High tEHWH 0 0 0 0 nS CE Pulse Width High tEHEL 20 20 20 20 nS Duration of Word Write Operation (1) (x32) tEHQV1 6 6 6 6 µS Duration of Erase Operation (Boot) (1) tEHQV2 0.3 0.3 0.3 0.3 Sec Duration of Erase Operation (Parameter) (1) tEHQV3 0.3 0.3 0.3 0.3 Sec Duration of Erase Operation (Main) (1) tEHQV4 0.6 0.6 0.6 0.6 Sec VPP Hold from Valid SRD (1) tQVVL 0 0 0 0 nS RP VHH Hold from Valid SRD (1) tQVPH 0 0 0 0 nS Boot Block Lock Delay (1) tPHBR 200 100 100 100 nS NOTES: 1. Sampled, but not 100% tested. 2. Performance at VCC = +4.5V to +5.5V is guaranteed. Performance at VCC = +3.3V is typical (Not Tested). AC Characteristics – Read Only Operations (TA = -55 °C to +125°C, VCC = +4.5V to + 5.5V(5V Operation), or +3.0V to +3.6V(3.3V Operation), Unless otherwise specified) Parameter Symbol JEDEC Standard +3.3V VCC (2) Typical +4.5V to +5.5V VCC Units 120nS Min Max 80nS Min Max 100nS Min Max 120nS Min Max Read Cycle Time tAVAV 120 80 100 120 nS Address to Output Delay tAVQV 120 80 100 120 nS CE to Output Delay tELQV 120 80 100 120 nS RP to Output Delay tPHQV 1.5 .45 .45 .45 µS OE to Output Delay tGLQV 65 40 40 40 nS CE to Output in Low Z (1) tELQX 0 0 0 0 nS CE to Output in High Z (1) tEHQZ 55 30 30 30 nS OE to Output in Low Z (1) tGLQX 0 0 0 0 nS OE to Output in High Z (1) tGHQZ 45 30 30 30 nS Output Hold from Address, CE, or OE Change, Whichever Occurs First (1) tOH 0 0 0 0 nS Notes: 1. Guaranteed by design, but not tested. 2. Performance at VCC = +4.5V to +5.5V is guaranteed. Performance at VCC = +3.3V is typical (Not Tested). |
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