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Agere Systems Inc.

1345-Type Receiver with

Data Sheet

Clock Recovery and Data Retiming

January 2000

PWB Layout Guidelines

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Follow high-speed ECL design rules.

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All high-speed output lines must be controlled-impedance lines, and the termination impedance must match

the line impedance. Controlled-impedance interruptions should be avoided (i.e., 90° bends, etc.) and paired lines

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Each output line should be terminated at the end of the line and must have a bypass capacitor on the voltage

side of the resistor for each termination.

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Data and clock output lines should be as short and as straight as possible and isolated from noise sources (and

each other) to prevent noise from feeding back into the receiver.

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Noise that couples into the receiver through the power supply pins can degrade device performance. See

Figure 2 for an example of power supply filtering for the receiver 5 V power supply pins.

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Use a multilayer board so that the ground plane surrounds the areas occupied by the receiver and directly under-

neath it. Directly attach all pins listed as ground pins to the ground plane with no additional lead length.

All unused outputs must be terminated as shown. All resistors are 1/8 W, thin-film, ceramic chips. All capacitors are

25 Vdc, ceramic X7R or equivalent.

Qualification and Reliability

To help ensure high product reliability and customer satisfaction, Agere Systems is committed to an intensive qual-

ity program that starts in the design phase and proceeds through the manufacturing process. Optoelectronics mod-

ules are qualified to Agere Systems internal standards using MIL-STD-883 test methods and procedures and using

sampling techniques consistent with

undergone an extensive and rigorous set of qualification tests. This qualification program fully meets the intent of

ment, and manufacturing facility of the Optoelectronics unit at Agere Systems is certified to be in full compliance

with the latest