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ACT-7000SC-240F17T Datasheet(PDF) 2 Page - Aeroflex Circuit Technology |
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ACT-7000SC-240F17T Datasheet(HTML) 2 Page - Aeroflex Circuit Technology |
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2 / 25 page  Aeroflex Circuit Technology SCD7000SC REV B 7/30/01 Plainview NY (516) 694-6700 2 DESCRIPTION The ACT 7000SC is a highly integrated symmetric superscalar microprocessor capable of issuing two instructions each processor cycle. It has two high performance 64-bit integer units as well as a high throughput, fully pipelined 64-bit floating point unit. To keep its multiple execution units running efficiently, the ACT 7000SC integrates not only 16KB 4-way set associative instruction and data caches but backs them up with an integrated 256KB 4-way set associative secondary as well. For maximum efficiency, the data and secondary caches are writeback and nonblocking. A RM52XX family compatible, operating system friendly memory management unit with a 64/ 48-entry fully associative TLB and a high-performance 64-bit system interface supporting hardware prioritized and vectored interrupts round out the main features of the processor. The ACT 7000SC is ideally suited for highend embedded control applications such as internetworking, high performance image manipulation, high speed printing, and 3-D visualization. HARDWARE OVERVIEW The ACT 7000SC offers a high-level of integration targeted at high-performance embedded applications. The key elements of the ACT 7000SC are briefly described below. CPU Registers Like all MIPS ISA processors, the ACT 7000SC CPU has a simple, clean user visible state consisting of 32 general purpose registers, or GPR’s, two special purpose registers for integer multiplication and division, and a program counter; there are no condition code bits. Figure 1 shows the user visible state. Superscalar Dispatch The ACT 7000SC has an efficient symmetric superscalar dispatch unit which allows it to issue up to two instructions per cycle. For purposes of instruction issue, the ACT 7000SC defines four classes of instructions: integer, load/store, branches, and floating-point. There are two logical pipelines, the function, or F, pipeline and the memory, or M, pipeline. Note however that the M pipe can execute integer as well as memory type instructions. Figure 2 is a simplification of the pipeline section and illustrates the basics of the instruction issue mechanism. Table 1 – Instruction Issue Rules F Pipe M Pipe one of: one of: integer, branch, floating-point, integer mul, div integer, load/store General Purpose Registers 63 0 Multiply/Divide Registers 063 0 r1 HI r2 63 0 •LO • • Program Counter •63 0 r29 PC r30 r31 Figure 1 – CP0 Registers |
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