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MMDF2N06V Datasheet(PDF) 1 Page - Motorola, Inc |
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MMDF2N06V Datasheet(HTML) 1 Page - Motorola, Inc |
1 / 4 page MMDF2N06V DUAL TMOS MOSFET 3.3 AMPERES 60 VOLTS RDS(on) = 0.115 OHM Source–1 1 2 3 4 8 7 6 5 Top View Gate–1 Source–2 Gate–2 Drain–1 Drain–1 Drain–2 Drain–2 D S G CASE 751–05, Style 11 SO–8 TM 1 Motorola TMOS Power MOSFET Transistor Device Data Product Preview TMOS V™ SO-8 for Surface Mount N–Channel Enhancement–Mode Silicon Gate TMOS V is a new technology designed to achieve an on–resis- tance area product about one–half that of standard MOSFETs. This new technology more than doubles the present cell density of our 50 and 60 volt TMOS devices. Just as with our TMOS E–FET designs, TMOS V is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. New Features of TMOS V • On–resistance Area Product about One–half that of Standard MOSFETs with New Low Voltage, Low RDS(on) Technology • Faster Switching than E–FET Predecessors Features Common to TMOS V and TMOS E–FETS • Avalanche Energy Specified • IDSS and VDS(on) Specified at Elevated Temperature • Static Parameters are the Same for both TMOS V and TMOS E–FET • Miniature SO–8 Surface Mount Package – Saves Board Space • Mounting Information for SO–8 Package Provided MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Value Unit Drain–to–Source Voltage VDSS 60 Vdc Drain–to–Gate Voltage, (RGS = 1 MΩ) VDGR 60 Vdc Gate–to–Source Voltage — Continuous VGS ± 20 Vdc Drain Current — Continuous @ TA = 25°C Drain Current — Continuous @ TA = 100°C Drain Current — Single Pulse (tp ≤ 10 µs) ID ID IDM 3.3 0.5 9.9 Adc Apk Total Power Dissipation @ TA = 25°C (1) PD 2.0 W Operating and Storage Temperature Range TJ, Tstg – 55 to 175 °C Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 3.3 Apk, L = 10 mH, RG = 25 Ω) EAS 54 mJ Thermal Resistance, Junction to Ambient (1) R θJA 62.5 °C/W Maximum Lead Temperature for Soldering Purposes, 0.0625 ″ from case for 10 seconds TL 260 °C DEVICE MARKING 2N06V (1) Mounted on G10/FR4 glass epoxy board using minimum recommended footprint. ORDERING INFORMATION Device Reel Size Tape Width Quantity MMDF2N06V1 7 ″ 12mm embossed tape 500 MMDF2N06V2 13 ″ 12mm embossed tape 2500 This document contains information on a new product. Specifications and information herein are subject to change without notice. E–FET and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. Order this document by MMDF2N06V/D MOTOROLA SEMICONDUCTOR TECHNICAL DATA © Motorola, Inc. 1996 |
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