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FOD8318R2 Datasheet(PDF) 2 Page - Fairchild Semiconductor |
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FOD8318R2 Datasheet(HTML) 2 Page - Fairchild Semiconductor |
2 / 31 page ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD8318 Rev. 1.1.2 2 Truth Table *VOUT is always LOW with ‘clamp’ being active (gate voltage < 2 V above VSS). Pin Definitions VIN+ VIN– UVLO (VDD2 – VE) DESAT Detected? FAULT VOUT* XX Active XX LOW XX X Yes LOW LOW LOW XXX X LOW X HIGH X X X LOW HIGH LOW Not Active No HIGH HIGH Pin # Name Description 1VIN+ Non-inverting gate drive control input 2VIN– Inverting gate drive control input 3VDD1 Positive input supply voltage (3 V to 5.5 V) 4 GND1 Input ground 5 RESET Fault reset input 6FAULT Fault output 7VLED1+ LED 1 anode (must be left unconnected) 8VLED1- LED 1 cathode (must be connected to ground) 9VSS Output supply voltage (negative) 10 VCLAMP Active Miller clamp supply voltage 11 VO Gate drive output voltage 12 VS Source of pull-up PMOS transistor 13 VDD2 Positive output supply voltage 14 DESAT Desaturation voltage input 15 VLED2+ LED 2 anode (must be left unconnected) 16 VE Output supply voltage / IGBT emitter 1 2 3 4 5 6 7 8 VIN+ VIN– VDD1 GND1 RESET FAULT VLED1+ VLED1- VE VLED2+ DESAT VDD2 VS VO VCLAMP VSS 16 15 14 13 12 11 10 9 |
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