UCC27528DSDR datasheet(4/31 Pages) TI

Part #	UCC27528DSDR

Description	Dual 5-A High-Speed Low-Side Gate Driver Based on CMOS Input Threshold Logic

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Manufacturer	TI [Texas Instruments]

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UCC27527

UCC27528

SLUSBD0B – DECEMBER 2012 – REVISED JANUARY 2013

www.ti.com

ELECTRICAL CHARACTERISTICS

VDD = 12 V, TA = TJ = -40°C to 140°C, 1-µF capacitor from VDD to GND. Currents are positive into, negative out of the

specified terminal (unless otherwise noted,)

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNITS

Bias Currents

VDD = 3.4 V,

INA=VDD,

55

125

225

Startup current,

INB=VDD

IDD(off)

(based on UCC27524 Input

μA

VDD = 3.4 V,

configuration)

INA=GND,

25

125

225

INB=GND

Under Voltage LockOut (UVLO)

TJ = 25°C

3.91

4.20

4.50

VON

Supply start threshold

TJ = -40°C to 140°C

3.75

4.20

4.65

V

Minimum operating voltage

VOFF

3.60

3.90

4.40

after supply start

VDD_H

Supply voltage hysteresis

0.20

0.30

0.50

Inputs (INA, INB, INA+, INA-, INB+, INB-), UCC2752X (D, DSD)

Output high for non-inverting input pins

VIN_H

Input signal high threshold

55

70

Output low for inverting input pins

Output low for non-inverting input pins

%VDD

VIN_L

Input signal low threshold

30

38

Output high for inverting input pins

VIN_HYS

Input hysteresis

17

Enable (ENA, ENB) UCC2752X (D, DSD)

VEN_H

Enable signal high threshold

Output enabled

1.7

1.9

2.1

VEN_L

Enable signal low threshold

Output disabled

0.95

1.10

1.25

V

VEN_HYS

Enable hysteresis

0.70

0.80

1.10

Outputs (OUTA, OUTB)

ISNK/SRC

Sink/source peak current(1)

CLOAD = 0.22 µF, FSW = 1 kHz

±5

A

VDD-VOH

High output voltage

IOUT = -10 mA

0.075

V

VOL

Low output voltage

IOUT = 10 mA

0.01

ROH

Output pull-up resistance(2)

IOUT = -10 mA

2.5

5

7.5

Ω

ROL

Output pull-down resistance

IOUT = 10 mA

0.15

0.5

1

Ω

Switching Time

tR

Rise time (3)

CLOAD = 1.8 nF, VDD = 10 V

7

tF

Fall time(3)

CLOAD = 1.8 nF, VDD = 10 V

6

Delay matching between 2

INA = INB, OUTA and OUTB at 50% transition

tM

1

4

channels

point, VDD = 10 V

Minimum input pulse width

ns

tPW

that changes the output

VDD = 10 V

15

state(3)

Input to output propagation

tD1, tD2

CLOAD = 1.8 nF, 7-V input pulse, VDD = 10 V

6

17

26

delay (3)

EN to output propagation

tD3, tD4

CLOAD = 1.8 nF, 7-V enable pulse, VDD = 10 V

6

13

23

delay (3)

(1)

Ensured by design.

(2)

ROH represents on-resistance of only the P-Channel MOSFET device in pull-up structure of UCC2752X output stage.

(3)

See timing diagrams in Figure 1, Figure 2, Figure 3 and Figure 4

4

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