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TPS23785BPWPR Datasheet(PDF) 11 Page - Texas Instruments

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Part # TPS23785BPWPR
Description  High-Power, High-Efficiency PoE PD and DC-to-DC Controller
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TPS23785BPWPR Datasheet(HTML) 11 Page - Texas Instruments

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TPS23785B
www.ti.com
SLUSB90A – DECEMBER 2012 – REVISED DECEMBER 2012
CLS
A resistor from CLS to VSS programs the classification current per the IEEE standard. The PD power ranges and
corresponding resistor values are listed in Table 1. The power assigned should correspond to the maximum
average power drawn by the PD during operation.
High-power PSEs may perform two-event classification if Class 4 is advertised by the PD. The TPS23785B
presents the same (resistor-programmed) class each cycle per the standard.
Table 1. Class Resistor Selection
PD INPUT POWER
RESISTOR
CLASS
NOTES
MINIMUM
MAXIMUM
(
Ω)
(W)
(W)
0
0.44
12.95
1270
Minimum may be reduced by pulsed loading. Serves as a catch-all default class.
1
0.44
3.84
243
2
3.84
6.49
137
3
6.49
12.95
90.9
4
12.95
25.5
63.4
Not allowed for IEEE 802.3-2008. Use to indicate a Type 2 PD (high power) per
IEEE 802.3at.
CS
The CS (current-sense) input for the dc/dc converter should be connected to the high side of the switching
MOSFET’s current sense resistor (RCS). The current-limit threshold, VCSMAX, defines the voltage on CS above
which the GATE ON time will be terminated regardless of the voltage on CTL.
The TPS23785B provides internal slope compensation (150 mV, VSLOPE), an output current for additional slope
compensation, a peak current limiter, and an off-time pull-down to this pin.
Routing between the current-sense resistor and the CS pin should be short to minimize cross-talk from noisy
traces such as the gate drive signal.
CTL
CTL (control) is the voltage-control loop input to the PWM (pulse width modulator). Pulling VCTL below VZDC (zero
duty cycle voltage) causes GATE to stop switching. Increasing VCTL above VZDC raises the switching MOSFET
programmed peak current. The maximum (peak) current is requested at approximately VZDC + (2 × VCSMAX). The
ac gain from CTL to the PWM comparator is 0.5 V/V. The total internal divider resistance from CTL to ARTN is
approximately 100 k
Ω.
Use VB as a pull up source for CTL.
Copyright © 2012, Texas Instruments Incorporated
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