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F28M36H33B2ZWTT Datasheet(PDF) 8 Page - Texas Instruments |
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F28M36H33B2ZWTT Datasheet(HTML) 8 Page - Texas Instruments |
8 / 202 page F28M36P63B2, F28M36P63C2 F28M36P53B2, F28M36P53C2, F28M36P33B2, F28M36P33C2 SPRS825 – OCTOBER 2012 www.ti.com 2.2 Memory Maps Section 2.2.1 shows the Control Subsystem Memory Map. Section 2.2.2 shows the Master Subsystem Memory Map. 2.2.1 Control Subsystem Memory Map Table 2-2. Control Subsystem M0, M1 RAM C Address Size C DMA Access(1) Control Subsystem M0, M1 RAM (x16 Aligned)(1) (Bytes) no 0000 0000 – 0000 03FF M0 RAM (ECC) 2K no 0000 0400 – 0000 07FF M1 RAM (ECC) 2K (1) The letter "C" refers to the Control Subsystem. Table 2-3. Control Subsystem Peripheral Frame 0 (Includes Analog) C Address Control Subsystem Peripheral Frame 0 Size C DMA Access(1) (x16 Aligned)(1) (Includes Analog) (Bytes) 0000 0800 – 0000 087F Reserved Control Subsystem Device Configuration Registers (Read no 0000 0880 – 0000 0890 34 Only) 0000 0891 – 0000 0ADF Reserved no 0000 0AE0 – 0000 0AEF C28x CSM Registers 32 0000 0AF0 – 0000 0AFF Reserved yes 0000 0B00 – 0000 0B0F ADC1 Result Registers 32 0000 0B10 – 0000 0B3F Reserved yes 0000 0B40 – 0000 0B4F ADC2 Result Registers 32 0000 0B50 – 0000 0BFF Reserved no 0000 0C00 – 0000 0C07 CPU Timer 0 16 no 0000 0C08 – 0000 0C0F CPU Timer 1 16 no 0000 0C10 – 0000 0C17 CPU Timer 2 16 0000 0C18 – 0000 0CDF Reserved no 0000 0CE0 – 0000 0CFF PIE Registers 64 no 0000 0D00 – 0000 0DFF PIE Vector Table 512 no 0000 0E00 – 0000 0EFF PIE Vector Table Copy (Read Only) 512 0000 0F00 – 0000 0FFF Reserved no 0000 1000 – 0000 11FF C28x DMA Registers 1K 0000 1200 – 0000 16FF Reserved no 0000 1700 – 0000 177F Analog Subsystem Control Registers 256 no 0000 1780 – 0000 17FF C Hardware Logic BIST Registers 256 0000 1800 – 0000 3FFF Reserved (1) The letter "C" refers to the Control Subsystem. 8 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback |
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