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DAC8512FS Datasheet(PDF) 6 Page - Analog Devices |
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DAC8512FS Datasheet(HTML) 6 Page - Analog Devices |
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6 / 20 page  DAC8512 –6– REV. A OUTPUT SECTION The rail-to-rail output stage of this amplifier has been designed to provide precision performance while operating near either power supply. VDD VOUT AGND N-CH P-CH Figure 4. Equivalent Analog Output Circuit Figure 4 shows an equivalent output schematic of the rail-to-rail amplifier with its N channel pull down FETs that will pull an output load directly to GND. The output sourcing current is provided by a P channel pull up device that can supply GND terminated loads, especially at the low supply tolerance values of 4.75 volts. Figures 5 and 6 provide information on output swing performance near ground and full-scale as a function of load. In addition to resistive load driving capability the amplifier has also been carefully designed and characterized for up to 500 pF ca- pacitive load driving capability. POWER SUPPLY The very low power consumption of the DAC8512 is a direct result of a circuit design optimizing use of the CBCMOS pro- cess. By using the low power characteristics of the CMOS for the logic, and the low noise, tight matching of the complemen- tary bipolar transistors good analog accuracy is achieved. For power consumption sensitive applications it is important to note that the internal power consumption of the DAC8512 is strongly dependent on the actual logic input voltage levels present on the SDI, CS, LD, and CLR pins. Since these inputs are standard CMOS logic structures they contribute static power dissipation dependent on the actual driving logic VOH and VOL voltage levels. The graph in Figure 9 shows the effect on to- tal DAC8512 supply current as a function of the actual value of input logic voltage. Consequently use of CMOS logic vs. TTL minimizes power dissipation in the static state. A VIL = 0 V on the SDI, CS and CLR pins provides the lowest standby power dissipation of 2.5 mW (500 µA × 5 V). As with any analog system, it is recommended that the DAC8512 power supply be bypassed on the same PC card that contains the chip. Figure 10 shows the power supply rejection versus frequen- cy performance. This should be taken into account when using higher frequency switched mode power supplies with ripple fre- quencies of 100 kHz and higher. One advantage of the rail-to-rail output amplifier used in the DAC8512 is the wide range of usable supply voltage. The part is fully specified and tested over temperature for operation from +4.75 V to +5.25 V. If reduced linearity and source current ca- pability near full scale can be tolerated, operation of the DAC8512 is possible down to +4.3 volts. The minimum operating supply voltage versus load current plot, in Figure 11, provides informa- tion for operation below VDD = +4.75 V. TIMING AND CONTROL The DAC8512 has a separate serial input register from the 12-bit DAC register that allows preloading of a new data value into the serial register without disturbing the present DAC out- put voltage. After the new value is fully loaded in the serial in- put register it can be asynchronously transferred to the DAC register by strobing the LD pin. The DAC register uses a level sensitive LD strobe that should be returned high before any new data is loaded into the serial input register. At any time the contents of the DAC register can be reset to zero by strobing the CLR pin which causes the DAC output voltage to go to zero volts. All of the timing requirements are detailed in Figure 1 along with the Table I Control-Logic Truth Table. |
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