DAC8412/DAC8413

–11–

REV. D

Table I. DAC8412/DAC8413 Logic Table

A1

A0

R/

W

CS

RS

LDAC

INPUT REG

OUTPUT REG

MODE

DAC

L

L

L

L

H

L

WRITE

WRITE

Transparent

A

L

H

L

L

H

L

WRITE

WRITE

Transparent

B

H

L

L

L

H

L

WRITE

WRITE

Transparent

C

H

H

L

L

H

L

WRITE

WRITE

Transparent

D

LL

LLH

H

WRITE

HOLD

WRITE INPUT

A

LH

LLH

H

WRITE

HOLD

WRITE INPUT

B

H

L

L

L

H

H

WRITE

HOLD

WRITE INPUT

C

H

H

L

L

H

H

WRITE

HOLD

WRITE INPUT

D

L

L

H

L

H

H

READ

HOLD

READ INPUT

A

L

H

H

L

H

H

READ

HOLD

READ INPUT

B

H

L

H

L

H

H

READ

HOLD

READ INPUT

C

H

H

H

L

H

H

READ

HOLD

READ INPUT

D

X

X

X

H

H

L

HOLD

Update all output registers

All

X

X

X

H

H

H

HOLD

HOLD

HOLD

All

X

X

X

X

L

X

*All registers reset to mid/zero-scale

All

XX

XH

g

X

*All registers latched to mid/zero-scale

All

*DAC8412 resets to midscale, and DAC8413 resets to zero scale. L = Logic Low; H = Logic High; X - Don’t Care. Input and Output registers are transparent when

asserted.

The R/

W input, when enabled by CS, controls the writing to and

reading from the input register.

Coding

Both the DAC8412 and DAC8413 use binary coding. The out-

put voltage can be calculated by:

VV

VV

N

OUT

REFL

REF H

REFL

=+

×

(_

)

4096

where N is the digital code in decimal.

RESET

The

RESET function can be used either at power-up or at any

time during the DAC’s operation. The

RESET function is inde-

pendent of

CS. This pin is active LOW and sets the DAC output

registers to either center code for the DAC8412, or zero code

for the DAC8413. The reset to center code is most useful when

the DAC is configured for bipolar references and an output of

zero volts after reset is desired.

Supplies

erating range is between +5 V and +15 V.

function. It is normally connected to +5 V. This pin is a logic

reference input only. It does not supply current to the device.

it does supply currents to the digital outputs when readback

is used.

Amplifiers

Unlike many voltage output DACs, the DAC8412 features buff-

ered voltage outputs. Each output is capable of both sourcing

and sinking 5 mA at

±10 volts, eliminating the need for external

amplifiers when driving 500 pF or smaller capacitive load in

most applications. These amplifiers are short-circuit protected.

Reference Inputs

inputs set the output high and low voltage limits of all four of

the DACs. Each reference input has voltage restrictions with

respect to the other reference and to the power supplies. The

current sinking capability and must be buffered with an ampli-

It is recommended that the reference inputs be bypassed with

0.2

µF capacitors when operating with ±10 V references. This

limits the reference bandwidth.

Digital I/O

See Table I for digital control logic truth table. Digital I/O consists

of a 12-bit bidirectional data bus, two registers select inputs, A0

and A1, a R/

W input, a RESET input, a Chip Select (CS), and

a Load DAC (

LDAC) input. Control of the DACs and bus

direction is determined by these inputs as shown in Table I.

Digital data bits are labeled with the MSB defined as data bit

“11” and the LSB as data bit “0.” All digital pins are TTL/

CMOS compatible.

See Figure 35 for a simplified I/O logic diagram. The register

select inputs A0 and A1 select individual DAC registers “A”

(binary code 00) through “D” (binary code 11). Decoding of

the registers is enabled by the

CS input. When CS is high no

decoding takes place, and neither the writing nor the reading of

the input registers is enabled. The loading of the second bank of

registers is controlled by the asynchronous

LDAC input. By tak-

ing

LDAC low while CS is enabled, all output registers can be

for updating all DACs is a minimum of 170 ns.