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DAC8143FS Datasheet(PDF) 7 Page - Analog Devices |
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DAC8143FS Datasheet(HTML) 7 Page - Analog Devices |
7 / 12 page DAC8143 –7– REV. C ESD PROTECTION The DAC8143 digital inputs have been designed with ESD resistance incorporated through careful layout and the inclusion of input protection circuitry. Figure 11 shows the input protection diodes. High voltage static charges applied to the digital inputs are shunted to the supply and ground rails through forward biased diodes. These protection diodes were designed to clamp the inputs well below dangerous levels during static discharge conditions. VDD DTL/TTL/CMOS INPUTS Figure 11. Digital Input Protection EQUIVALENT CIRCUIT ANALYSIS Figures 12 and 13 show equivalent circuits for the DAC8143’s internal DAC with all bits LOW and HIGH, respectively. The reference current is switched to IOUT2 when all data bits are LOW, and to IOUT1 when all bits are HIGH. The ILEAKAGE current source is the combination of surface and junction leakages to the substrate. The 1/4096 current source represents the constant 1-bit current drain through the ladder’s terminating resistor. Output capacitance is dependent upon the digital input code. This is because the capacitance of a MOS transistor changes with applied gate voltage. This output capacitance varies be- tween the low and high values. RFEEDBACK IOUT1 IOUT2 R = 10k ILEAKAGE 60pF ILEAKAGE 90pF 1/4096 R = 10k IREF VREF Figure 12. Equivalent Circuit (All Inputs LOW) IOUT2 ILEAKAGE 60pF RFEEDBACK IOUT1 R = 10k ILEAKAGE 90pF 1/4096 R = 10k IREF VREF Figure 13. Equivalent Circuit (All Inputs HIGH) DYNAMIC PERFORMANCE ANALOG OUTPUT IMPEDANCE The output resistance, as in the case of the output capacitance, varies with the digital input code. This resistance, looking back into the IOUT1 terminal, varies between 11 kΩ (the feedback resistor alone when all digital input are LOW) and 7.5 k Ω (the feedback resistor in parallel with approximately 30 k Ω of the R-2R ladder network resistance when any single bit logic is HIGH). Static accuracy and dynamic performance will be af- fected by these variations. The gain and phase stability of the output amplifier, board layout, and power supply decoupling will all affect the dynamic performance of the DAC8143. The use of a small compensation capacitor may be required when high speed operational amplifi- ers are used. It may be connected across the amplifier’s feed- back resistor to provide the necessary phase compensation to critically damp the output. The considerations when using high speed amplifiers are: 1. Phase compensation (see Figures 16 and 17). 2. Power supply decoupling at the device socket and use of proper grounding techniques. OUTPUT AMPLIFIER CONSIDERATIONS When using high speed op amps, a small feedback capacitor (typically 5 pF–30 pF) should be used across the amplifiers to minimize overshoot and ringing. For low speed or static applications, ac specifications of the amplifier are not very criti- cal. In high speed applications, slew rate, settling time, open- loop gain and gain/phase margin specifications of the amplifier should be selected for the desired performance. It has already been noted that an offset can be caused by including the usual bias current compensation resistor in the amplifier’s noninvert- ing input terminal. This resistor should not be used. Instead, the amplifier should have a bias current that is low over the tem- perature range of interest. Static accuracy is affected by the variation in the DAC’s output resistance. This variation is best illustrated by using the circuit of Figure 14 and the equation: VERROR = VOS 1+ RFB RO VOS VREF RR R ETC RFB R2 R2 R2 OP-77 Figure 14. Simplified Circuit |
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