Internal

Band Gap

Referance

Current Limiting

OTG Switch

DET

VBUS Detection

+

OVLO

UVLO

Control Logic

+

Charge Pump

ADJ

FLT

EN

GND

D+

D–

ID

TPD4S214

SLVSBR1A – JANUARY 2013 – REVISED FEBRUARY 2013

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

ORDERABLE PART

TOP-SIDE MARKING

NUMBER

–40°C to 85°C

WCSP – YFF (0.4-mm pitch)

Tape and reel

TPD4S214YFFR

B3214

(1)

Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

(2)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

Web site at www.ti.com.

CIRCUIT SCHEMATIC DIAGRAM

Figure 1. Circuit Schematic

2

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Product Folder Links: TPD4S214