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SN65DSI85ZQE Datasheet(PDF) 10 Page - Texas Instruments |
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SN65DSI85ZQE Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 45 page  DSI lane A_CLKP/N (LVDS_CHA_CLK) tdis t en ULPS (LP00) State A_CLKP/N (LVDS_CHA_CLK) tdis t en DA/BC_P/N (DSI_Clk_Input) Init seq 2 Treset (Reset Time) DA/B*_P/N (DSI_Data_Input) EN LP11 LP11 VCC 1.65 - 1.95 V 1 ms Init seq 4 Init seq 5 Init seq 7 Int seq 6 t0-6 VOD(H) VOD(L) 0.00V CLK Yn t1 t2 t3 t4 t5 t6 t0 SN65DSI85 SLLSEB9C – SEPTEMBER 2012 – REVISED DECEMBER 2012 www.ti.com Figure 4. SN65DSI85 FlatLink™ Timing Definitions (1) The Initialization sequence can be found at Recommended Initialization Sequence section of this document. The “Init seq*” corresponds to the sequence number in the Recommended Initialization Sequence section. (2) A_CLKP/N(LVDS_CHA_CLK) becomes active along with CHA LVDS data lanes0-2 after PLL lock event occurs and CLK source(REF_CLK or DSI HS CLK) is active(Init seq7). Other LVDS CLK/data lanes stay low until they are configured to be enabled in corresponding CSRs (3) The LP11 to HS transition to the data lanes and the CLK lane MUST be done per the timing requirements specified in the MIPI® D-PHY Specification. Figure 5. RESET and Initalization Timing Definition While VCC is High (1) See the ULPS section of the data sheet for the ULPS entry and exit sequence. (2) ULPS entry and exit protocol and timing requirements must be met per MIPI® DPHY specification. Figure 6. ULPS Timing Definition 10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: SN65DSI85 |
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