ONET1151M

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SLLSED8 – OCTOBER 2012

DETAILED DESCRIPTION

EQUALIZER

The data signal is applied to an input equalizer by means of the input signal pins DIN+ / DIN–, which provide on-

chip differential 100-

Ω line-termination. The equalizer is enabled by setting EQENA to 1 (bit 1 of register 0).

Equalization of up to 300-mm (12 in.) of microstrip or stripline transmission line on FR4 printed circuit boards can

be achieved. The amount of equalization is digitally controlled by the 2-wire interface and control logic block and

is dependant on the register settings EQADJ[0..7] (register 3). The equalizer can be turned off and bypassed by

setting EQENA to 0. For details about the equalizer settings, see Table 16.

LIMITER

By limiting the output signal of the equalizer to a fixed value, the limiter removes any overshoot after the input

equalization and provides the input signal for the output driver. Adjustments to the limiter bias current and emitter

follower current can be made to trade off the rise and fall times and supply current. The limiter bias current is

adjusted through LIMCSGN (bit 7 of register 6) and LIMC[0..2] (bits 4, 5 and 6 of register 6). The emitter follower

current is adjusted through EFCSGN (bit 3 of register 6) and EFC[0..2] (bits 0, 1 and 2 of register 6). In addition,

the slope of the emitter follower current can be modified with the EFCRNG bit (bit 3 of register 5). Setting

EFCRNG to 1 results in a steeper slope.

HIGH-SPEED OUTPUT DRIVER

The modulation current is sunk from the common emitter node of the limiting output driver differential pair by

means of a modulation current generator, which is digitally controlled by the 2-wire serial interface. The collector

nodes of the output stages are connected to the output pins OUT+ and OUT–. The collectors have internal active

back termination. The outputs are optimized to drive a 50-

Ω single-ended load and to obtain the maximum

termination emitter follower current is adjusted through ABTSGN (bit 3 of register 7) and ABTEF[0..2] (bits 0, 1

and 2 of register 7). ABTUP (bit 7 of register 7) and ABTDWN (bit 6 of register 7) can control the active back

termination auxiliary buffer amplitude. Setting ABTUP to 1 increases the amplitude and setting ABTDWN to 1

decreases the amplitude. For most instances, these settings may be left in the default mode.

For waveform shaping, output pre-emphasis can be enabled by setting PKENA to 1 (bit 5 of register 0) and

adjusting the peaking height through PEADJ[0..3] (register 2).

In addition, the polarity of the output pins can be inverted by setting the output polarity switch bit, POL (bit 2 of

register 0) to 1.

MODULATION CURRENT GENERATOR

The modulation current generator provides the current for the current modulator described above. The

modulation current generator is controlled by applying an analog voltage in the range of 0 to 2.5 V to the AMP

pin, or it can be digitally controlled by the 2-wire interface block. The default method of control is through the

AMP pin. To digitally control the output amplitude set AMPCTRL (bit 0 of register 0) to 1.

An 8-bit wide control bus, AMP[0..7] (register 1), can be used to set the desired modulation current, and

therefore, the output voltage.

To decrease the output amplitude by approximately 18% set OARNG to 1 (bit 7 of register 5), to increase it by

OASH1 (bit 6 of register 5) to 1.

The modulation current, and therefore the output signal, can be disabled by setting the DIS input pin to a high

level or by setting ENA to 0 (bit 7 of register 0).

Copyright © 2012, Texas Instruments Incorporated

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