ISL95873

11

FN8390.0

December 10, 2012

Figure 13 shows the overcurrent set circuit. The inductor consists

of inductance L and the DC resistance DCR. The inductor DC

Equation 4:

given by Equation 5:

The DC voltage difference between the OCSET pin and the VO pin,

given by Equation 6:

The IC monitors the voltage of the OCSET pin and the VO pin.

When the voltage of the OCSET pin is higher than the voltage of

the VO pin for more than 10µs, an OCP fault latches the

converter off.

written as:

Where:

setpoint

fault detection circuit

- DCR is the inductor DC resistance

sense the inductor current. To sense the inductor current

correctly not only in DC operation, but also during dynamic

then written as Equation 8:

For example, if L is 1.5µH, DCR is 4.5m

When an OCP fault is declared, the converter will be latched off and

the PGOOD pin will be asserted low. The fault will remain latched

until the EN pin has been pulled below the falling EN threshold

Overvoltage

The overvoltage (OV) detection circuit triggers after the FB pin

than 2µs. For example, if the converter is programmed to regulate

1.0V at the FB pin, that voltage would have to rise above the typical

numerical terms, that would be 116% x 1.0V = 1.16V. When an OV

is detected, the converter will take PGOOD low and continue to

switching. The converter is not latched off. When the converter

output voltage drops below the falling overvoltage threshold,

OV detection is considered cleared.

means if the FB pin voltage falls below 102% x 1.0V = 1.02V for

more than 2µs, the controller will return PGOOD high. Figure 14

shows a simple illustration of PGOOD operation during an OV

detection event. The cross hatch portion of the PGOOD waveform

shown represents the 2µs recognition time prior to the PGOOD

transition.

Undervoltage

The UVP fault detection circuit triggers after the FB pin voltage is

example, if the converter is programmed to regulate 1.0V at the FB

threshold of 84% for more than 2µs in order to trip the UVP fault

latch. In numerical terms, that would be 84% x 1.0V = 0.84V.

When a UVP fault is declared, the converter will be latched off and

the PGOOD pin will be asserted low. The fault will remain latched

until the EN pin has been pulled below the falling EN threshold

FIGURE 13. OVERCURRENT PROGRAMMING CIRCUIT

PHASE

L

OCSET

VO

DCR

8.5µA

+

_

+

_

V

DCR

I

⋅

=

(EQ. 4)

V

ROCSET

8.5

μAR

OCSET

⋅

=

(EQ. 5)

V

OCSET

V

–

VO

V

–

ROCSET

I

⋅

I

⋅

–

==

(EQ. 6)

(EQ. 7)

R

OCSET

I

⋅

I

OCSET

----------------------------

=

(EQ. 8)

C

SEN

L

R

⋅

------------------------------------------

=

FIGURE 14. OVERVOLTAGE OPERATION

ENABLE

CCM/DCM OPERATION

MOSFET

PGOOD

VOUT

116%

102%