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DRV595DAP Datasheet(PDF) 3 Page - Texas Instruments |
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DRV595DAP Datasheet(HTML) 3 Page - Texas Instruments |
3 / 24 page FAULTZ SDZ SYNC FS0 FS1 Hi-Z GND GND GVDD IN– GVDD IN+ AVCC OUTP PVCC BSN GND OUTN PVCC OUTN BSN PVCC OUTP BSP MODSEL BSP GND GND PVCC GND GAIN/SLV FS2 32 31 30 29 19 13 14 15 16 17 18 20 1 2 3 4 5 6 7 8 9 10 11 12 21 22 23 24 28 27 26 25 Thermal PAD Bottom DRV595 www.ti.com SLOS808 – DECEMBER 2012 PINOUT CONFIGURATION DRV595 32-PIN HTSSOP Package (DAP) (Top View) Pin Functions PIN TYPE DESCRIPTION NO. NAME 1 MODSEL I Mode selection logic input (LOW = BD mode, HIGH = 1SPW mode). TTL logic levels with compliance to AVCC. 2 SDZ I Shutdown logic input (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels with compliance to AVCC. 3 FAULTZ DO General fault reporting. Open drain. See Table 3 FAULTZ = High, normal operation FAULTZ = Low, fault condition 4 IN+ I Positive differential input. Biased at 3 V. 5 IN– I Negative differential input. Biased at 3 V. 6, 7 GVDD PO Internally generated gate voltage supply. Not to be used as a supply or connected to any component other than a 1 µF X7R ceramic decoupling capacitor and the GAIN/SLV resistor divider. 8 GAIN/SLV I Selects Gain and selects between Master and Slave mode depending on pin voltage divider. 9, 10, 11 GND G Ground 12 Hi-Z I Input for fast disable/enable of outputs (HIGH = outputs Hi-Z, LOW = outputs enabled). TTL logic levels with compliance to AVCC. 13 FS2 I Frequency Selection input, used to select oscillator frequencies from 400kHz to 1200kHz. 14 FS1 I Frequency Selection input, used to select oscillator frequencies from 400kHz to 1200kHz. 15 FS0 I Frequency Selection input, used to select oscillator frequencies from 400kHz to 1200kHz. 16 SYNC DIO Clock input/output for synchronizing multiple devices. Direction determined by GAIN/SLV terminal. 17 AVCC P Analog Supply, can be connected to PVCC for single power supply operation. 18, 19 PVCC P Power supply 20, 24 BSN BST Boot strap for negative output, connect to 220 nF X5R, or better ceramic cap to OUTN 21 OUTN PO Negative output 22 GND G Ground 23 OUTN PO Negative output 25 GND G Ground Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: DRV595 |
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