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ADS42B49IRGCT Datasheet(PDF) 7 Page - Texas Instruments |
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ADS42B49IRGCT Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 66 page  ADS42B49 www.ti.com SBAS558B – DECEMBER 2012 – REVISED JANUARY 2013 DIGITAL CHARACTERISTICS At AVDD = 1.9 V, AVDD_BUF = 3.3 V, and DRVDD = 1.8 V, unless otherwise noted. DC specifications refer to the condition where the digital outputs do not switch, but are permanently at a valid logic level '0' or '1'. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, CTRL1, CTRL2, CTRL3)(1) VIH High-level input voltage All digital inputs support 1.3 V 1.8-V and 3.3-V CMOS VIL Low-level input voltage 0.4 V logic levels SDATA, SCLK(2) VHIGH = 1.8 V 10 µA IIH High-level input current SEN(3) VHIGH = 1.8 V 0 µA SDATA, SCLK VLOW = 0 V 0 µA IIL Low-level input current SEN VLOW = 0 V 10 µA DIGITAL OUTPUTS, CMOS INTERFACE (DA[13:0], DB[13:0], CLKOUT, SDOUT) DRVDD – VOH High-level output voltage DRVDD V 0.1 VOL Low-level output voltage 0 0.1 V CO Output capacitance (internal to device) pF DIGITAL OUTPUTS, LVDS INTERFACE With an external VODH High-level output differential voltage 275 350 425 mV 100- Ω termination With an external VODL Low-level output differential voltage –425 –350 –275 mV 100- Ω termination VOCM Output common-mode voltage 0.9 1.05 1.25 V (1) SCLK, SDATA, and SEN function as digital input pins in serial configuration mode. (2) SDATA and SCLK have an internal 150-k Ω pull-down resistor. (3) SEN has an internal 150-k Ω pull-up resistor to AVDD. Because the pull-up resistor is weak, SEN can also be driven by 1.8-V or 3.3-V CMOS buffers. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: ADS42B49 |
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