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ADV7170 Datasheet(PDF) 25 Page - Analog Devices

Part No. ADV7170
Description  Digital PAL/NTSC Video Encoder with 10-Bit SSAF™ and Advanced Power Management
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Maker  AD [Analog Devices]
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ADV7170/ADV7171
–25–
REV. 0
Genlock Control (MR22–MR21)
These bits control the genlock feature of the ADV7170/ADV7171.
Setting MR21 to a Logic “1” configures the SCRESET/RTC
pin as an input. Setting MR22 to Logic Level “0” configures
the SCRESET/RTC pin as a subcarrier reset input. Therefore,
the subcarrier will reset to Field 0 following a high-to-low tran-
sition on the SCRESET/RTC pin. Setting MR22 to Logic Level
“1” configures the SCRESET/RTC pin as a real-time control
input.
Active Video Line Control (MR23)
This bit switches between two active video line durations. A
zero selects ITU-R BT.470 (720 pixels PAL/NTSC) and a one
selects ITU-R/SMPTE “analog” standard for active video dura-
tion (710 pixels NTSC 702 pixels PAL).
Chrominance Control (MR24)
This bit enables the color information to be switched on and off
the video output.
Burst Control (MR25)
This bit enables the burst information to be switched on and off
the video output.
Low Power Control (MR26)
This bit enables the lower power mode of the ADV7170/ADV7171.
This will reduce the DAC current by 45%.
Reserved (MR27)
A Logical 0 must be written to this bit.
MODE REGISTER 3 MR3 (MR37–MR30)
(Address [SR4–SR0] = 03H)
Mode Register 3 is an 8-bit-wide register.
Figure 41 shows the various operations under the control of
Mode Register 3.
MR3 BIT DESCRIPTION
Revision Code (MR30–MR31)
This bit is read only and indicates the revision of the device.
VBI Pass-Through Control (MR32)
This bit determines whether or not data in the vertical blanking
interval (VBI) is output to the analog outputs or
BLANKed.
DAC Switching Control (MR33)
This bit is used to switch the DAC outputs from SCART to a
EUROSCART configuration. A complete table of all DAC
output configurations is shown below.
Chroma Output Select (MR34)
With this active high bit it is possible to output YUV data with a
composite output on the fourth DAC or a chroma output on the
fourth DAC (0 = CVBS; 1 = CHROMA)
Teletext Enable (MR35)
This bit must be set to “1” to enable teletext data insertion on
the TTX pin.
Teletext Mode Control (MR36)
This bit enables switching of the teletext request signal from a
continuous high signal (“MR36 = 0”) to a bit wise request sig-
nal (“MR36 = 1”).
Input Default Color (MR37)
This bit determines the default output color from the DACs for
zero input pixel data (or disconnected). A Logical “0” means
that the color corresponding to 00000000 will be displayed. A
Logical “1” forces the output color to black for 00000000 pixel
input video data.
Table II. DAC Output Configuration Matrix
MR34
MR40
MR41
MR33
DAC A
DAC B
DAC C
DAC D
Simultaneous Output
0000
CVBS
CVBS
C
Y
2 Composite and Y/C
0001Y
CVBS
C
CVBS
2 Composite and Y/C
0010
CVBS
CVBS
C
Y
2 Composite and Y/C
0011Y
CVBS
C
CVBS
2 Composite and Y/C
0100
CVBS
B
R
G
RGB and Composite
0101G
B
R
CVBS
RGB and Composite
0110
CVBS
U
V
Y
YUV and Composite
0111Y
U
V
CVBS
YUV and Composite
1000C
CVBS
C
Y
1 Composite, Y and 2C
1001Y
CVBS
C
C
1 Composite, Y and 2C
1010C
CVBS
C
Y
1 Composite, Y and 2C
1011Y
CVBS
C
C
1 Composite, Y and 2C
1100C
B
R
G
RGB and C
1101G
B
R
C
RGB and C
1110C
U
V
Y
YUV and C
1111Y
U
V
C
YUV and C
CVBS: Composite Video Baseband Signal
Y:
Luminance Component Signal (For YUV or Y/C Mode)
C:
Chrominance Signal (For Y/C Mode)
U:
Chrominance Component Signal (For YUV Mode)
V:
Chrominance Component Signal (For YUV Mode)
R:
RED Component Video (For RGB Mode)
G:
GREEN Component Video (For RGB Mode)
B:
BLUE Component Video (For RGB Mode)
NOTE
Each DAC can be powered ON or OFF individually with the following control
bits (“0” = ON, “1” = OFF).
MR13-DAC C
MR14-DAC D
MR15-DAC B
MR16-DAC A




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