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ADSP-21MSP5859 Datasheet(PDF) 3 Page - Analog Devices |
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ADSP-21MSP5859 Datasheet(HTML) 3 Page - Analog Devices |
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3 / 40 page  ADSP-21msp58/59 REV. 0 –3– seven wait states are automatically generated. This allows, for example, a 38 ns ADSP-21msp58/59 to use a 250 ns EPROM as external boot memory. Multiple programs can be selected and loaded from the EPROM with no additional hardware. The on-chip program memory can also be initialized through the HIP. The ADSP-21msp58/59 features a general purpose flag output whose state is controlled through software. You can use this output to signal an event to an external device. In addition, the data input and output pins on SPORT1 can be alternatively configured as an input and an output flag. A programmable interval timer can generate periodic interrupts. A 16-bit count register (TCOUNT) is decremented every n cycles, where n–1 is a scaling value stored in an 8-bit register (TSCALE). When the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (TPERIOD). The ADSP-21msp58/59 instruction set provides flexible data moves and multifunction (one or two data moves with a compu- tation) instructions. Every instruction can be executed in a single processor cycle. The ADSP-21msp58/59 uses an alge- braic syntax for ease of coding and readability. A comprehensive set of development tools supports program development. Serial Ports The ADSP-21msp58/59 processors include two synchronous se- rial ports (SPORT0 and SPORT1) for serial communications and multiprocessor communication. Here is a brief list of the capabilities of the ADSP-21msp58/59 SPORTs. Refer to the ADSP-2100 Family User’s Manual for fur- ther details. • SPORTs are bidirectional with a separate, double-buffered transmit and receive section. • SPORTs can use an external serial clock or generate their own clock internally. • SPORTs have independent framing for the transmit and receive sections. Sections run in a frameless mode or with frame synchronization signals internally or externally gener- ated. Frame sync signals are programmed to be active high or low, with either of two pulse widths and timings. • SPORTs support serial data word lengths from 3 to 16 bits and provide optional A-law and µ-law companding according to CCITT recommendation G.711. • SPORTs receive and transmit sections generate separate interrupts when the SPORTs are ready to read or write new data. • SPORTs can receive and transmit an entire circular buffer of data with only one overhead cycle per data word (Autobuffering Mode). An interrupt is generated after a complete data buffer transfer. • SPORT0 has a multichannel interface to selectively receive and transmit a 24- or 32-word, time-division multiplexed serial bit stream. • SPORT1 can be reconfigured as two external interrupt inputs (IRQ0 and IRQ1) and the Flag In and Flag Out signals (FI, FO). The internally generated serial clock may still be used in this configuration. Pin Descriptions The ADSP-21msp58 and ADSP-21msp59 are available in a 100-lead TQFP package. Table I contains the pin descriptions. Table I. ADSP-21msp58/59 Pin List Pin # Group of Input/ Name Pins Output Function Digital Pins Address 14 O Address output for program, data and boot memory spaces Data 24 I/O Data I/O pins for program and data memories. Input only for boot memory space, with two MSBs used as boot space addresses. RESET 1 I Processor reset input IRQ2 1 I External interrupt request #2 BR 1 I External bus request input BG 1 O External bus grant output PMS 1 O External program memory select DMS 1 O External data memory select BMS 1 O Boot memory select RD 1 O External memory read enable WR 1 O External memory write enable MMAP 1 I Memory map select CLKIN, XTAL 2 I External clock or quartz crystal input CLKOUT 1 O Processor clock output HACK 1 O HIP acknowledge output HSEL 1 I HIP select input BMODE 1 I Boot mode select (0 = Standard EPROM Booting, 1 = HIP Booting) HMD0 1 I Bus strobe select (0 = RD/WR, 1 = RW/DS) HMD1 1 I HIP address/data mode select (0 = Separate, 1 = Multiplexed) HRD /HRW 1 I HIP read strobe or read/write select HWR /HDS 1 I HIP write strobe or host data strobe select HD7–0/ HAD7–0 8 I/O HIP data or HIP data and address HA2/ALE 1 I Host address 2 or address latch enable HA1–0/ (unused) 2 I Host address 1 and 0 inputs SPORT0 5 I/O Serial port 0 pins (TFS0, RFS0, DT0, DR0, SCLK0) SPORT1 5 I/O Serial port 1 pins (TFS1, RFS1, DT1, DR1, SCLK1) or |
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