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ADSP-21MSP5859 Datasheet(PDF) 8 Page - Analog Devices |
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ADSP-21MSP5859 Datasheet(HTML) 8 Page - Analog Devices |
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8 / 40 page  REV. 0 –8– ADSP-21msp58/59 wait-state configuration, host interface port, codec, and serial port operations are located in this region of memory. The remaining 12K of data memory is external. External data memory is divided into three zones, each associated with its own wait-state generator. By mapping peripherals into different zones, you can accommodate peripherals with different wait- state requirements. All zones default to seven wait states after RESET . For compatibility with other ADSP-2100 Family processors, bit definitions for DWAIT3 and DWAIT4 are shown in the Data Memory Wait State Control register, but they are not used by the ADSP-21msp58/59. 12K EXTERNAL MEMORY MAPPED REGISTERS AND RESERVED 0000 07FF 0800 3FFF 0000 37FF 3800 3FFF DATA MEMORY WAIT STATES DWAIT0 (1K EXTERNAL) DWAIT1 (1K EXTERNAL) DWAIT2 (10K EXTERNAL) NO WAIT STATES 03FF 0400 2FFF 3000 2K INTERNAL 1K RESERVED 2FFF 3000 3BFF 3C00 Figure 7. ADSP-21msp58/59 Data Memory Maps Boot Memory Interface The ADSP-21msp58/59 can load on-chip memory from exter- nal boot memory space. The boot memory space consists of 64K by 8-bit space, divided into eight separate 8K by 8-bit pages. Three bits in the System Control Register select which page is loaded by the boot memory interface. Another bit in the System Control Register allows the user to force a boot loading sequence under software control. Boot loading from Page 0 after RESET is initiated automatically if MMAP = 0. The boot memory interface can generate zero to seven wait states; it defaults to seven wait states after RESET. This allows the ADSP-21msp58/59 to boot from a single low cost EPROM such as a 27C256. Program memory is booted one byte at a time and converted to 24-bit program memory words. The BMS and RD signals are used to select and to strobe the boot memory interface. Only 8-bit data is read over the data bus, on pins D8–D15. To accommodate addressing up to eight pages of boot memory, the two MSBs of the data bus are used in the boot memory interface as the two MSBs of the boot memory address. The ADSP-2100 Family Assembler and Linker support the cre- ation of programs and data structures requiring multiple boot pages during execution. RD and WR must always be qualified by PMS, DMS, or BMS to ensure the correct program, data, or boot memory accessing. HIP Booting The ADSP-21msp58/59 can also boot programs through the Host Interface Port. If BMODE = 1 and MMAP = 0, the ADSP-21msp58/59 boots from the HIP. If BMODE = 0, the ADSP-21msp58/59 boots through the data bus (in the same way as the ADSP-2101), as described above in “Boot Memory Interface.” For additional information about HIP booting, refer to the ADSP-2100 Family User’s Manual, Chapter 7, “Host In- terface Port.” The ADSP-2100 Family Development Software includes a utility program called the HIP Splitter. This utility allows the creation of programs that can be booted through the ADSP- 21msp58/59 HIP, in a similar fashion as EPROM-bootable programs generated by the PROM Splitter utility. Bus Request and Bus Grant The ADSP-21msp58/59 can relinquish control of the data and address buses to an external device. When the external device requires access to memory, it asserts the bus request signal (BR). If the ADSP-21msp58/59 is not performing an external memory access, it responds to the active BR input in the follow- ing processor cycle by • three-stating the data and address buses and the PMS, DMS, BMS , RD, and WR output drivers, • asserting the bus grant (BG) signal, and • halting program execution. If GoMode is enabled, the ADSP-21msp58/59 will not halt pro- gram execution until it encounters an instruction that requires an external memory access. If the ADSP-21msp58/59 is performing an external memory ac- cess when the external device asserts the BR signal, then it will not three-state the memory interfaces or assert the BG signal until the cycle after the access is completed, which can be up to eight cycles later depending on the number of wait states. The instruction does not need to be completed when the bus is granted. If a single instruction requires two external memory accesses, the bus will be granted between the two accesses. When the BR signal is released, the processor releases the BG signal, which reenables the output drivers, and continues pro- gram execution from the point where it stopped. The bus request feature operates at all times, including when the processor is booting and when RESET is active. LOW POWER OPERATION The ADSP-21msp58/59 has three low power modes that signifi- cantly reduce the power dissipation when the device operates under standby conditions. These modes are: • Powerdown • Idle • Slow Idle The CLKOUT pin may also be disabled to reduce external power dissipation. The CLKOUT pin is controlled by Bit 14 of SPORT0 Autobuffer Control Register, DM[0x3FF3]. Powerdown The ADSP-21msp58/59 has a low power feature that lets the processors enter a very low power dormant state through hard- ware or software control. Here is a brief list of powerdown fea- tures. Refer to the ADSP-2100 Family User’s Manual, Chapter 9, |
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