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ADSP-2186LBCA-160 Datasheet(PDF) 10 Page - Analog Devices |
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ADSP-2186LBCA-160 Datasheet(HTML) 10 Page - Analog Devices |
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10 / 34 page  ADSP-2186L –10– REV. A The DSP memory address is latched and then automatically incre- mented after each IDMA transaction. An external device can therefore access a block of sequentially addressed memory by specifying only the starting address of the block. This increases throughput as the address does not have to be sent for each memory access. IDMA Port access occurs in two phases. The first is the IDMA Address Latch cycle. When the acknowledge is asserted, a 14-bit address and 1-bit destination type can be driven onto the bus by an external device. The address specifies an on-chip memory location, the destination type specifies whether it is a DM or PM access. The falling edge of the address latch signal latches this value into the IDMAA register. Once the address is stored, data can then either be read from or written to the ADSP-2186L’s on-chip memory. Asserting the select line ( IS) and the appropriate read or write line (IRD and IWR respectively) signals the ADSP-2186L that a particular transaction is required. In either case, there is a one-processor- cycle delay for synchronization. The memory access consumes one additional processor cycle. Once an access has occurred, the latched address is automati- cally incremented and another access can occur. Through the IDMAA register, the DSP can also specify the starting address and data format for DMA operation. Bootstrap Loading (Booting) The ADSP-2186L has two mechanisms to allow automatic loading of the internal program memory after reset. The method for booting is controlled by the Mode A, B and C configuration bits as shown in Table VI. These four states can be compressed into two-state bits by allowing an IDMA boot with Mode C = 1. However, three bits are used to ensure future compatibility with parts containing internal program memory ROM. BDMA Booting When the MODE pins specify BDMA booting, the ADSP-2186L initiates a BDMA boot sequence when RESET is released. The BDMA interface is set up during reset to the following de- faults when BDMA booting is specified: the BDIR, BMPAGE, BIAD and BEAD registers are set to 0; the BTYPE register is set to 0 to specify program memory 24-bit words; and the BWCOUNT register is set to 32. This causes 32 words of on- chip program memory to be loaded from byte memory. These 32 words are used to set up the BDMA to load in the remaining program code. The BCR bit is also set to 1, which causes program execution to be held off until all 32 words are loaded into on-chip program memory. Execution then begins at address 0. The ADSP-2100 Family development software (Revision 5.02 and later) fully supports the BDMA booting feature and can generate byte memory space compatible boot code. The IDLE instruction can also be used to allow the processor to hold off execution while booting continues through the BDMA interface. For BDMA accesses while in Host Mode, the ad- dresses to boot memory must be constructed externally to the ADSP-2186L. The only memory address bit provided by the processor is A0. Table VI. Boot Summary Table MODE C MODE B MODE A Booting Method 0 0 0 BDMA feature is used to load the first 32 program memory words from the byte memory space. Program execution is held off until all 32 words have been loaded. Chip is configured in Full Memory Mode. 010No Automatic boot opera- tions occur. Program execu- tion starts at external memory location 0. Chip is config- ured in Full Memory Mode. BDMA can still be used but the processor does not auto- matically use or wait for these operations. 1 0 0 BDMA feature is used to load the first 32 program memory words from the byte memory space. Program execution is held off until all 32 words have been loaded. Chip is configured in Host Mode. Additional interface hardware is required. 101IDMA feature is used to load any internal memory as de- sired. Program execution is held off until internal pro- gram memory location 0 is written to. Chip is configured in Host Mode. IDMA Booting The ADSP-2186L can also boot programs through its Internal DMA port. If Mode C = 1, Mode B = 0, and Mode A = 1, the ADSP-2186L boots from the IDMA port. The IDMA feature can load as much on-chip memory as desired. Program execu- tion is held off until on-chip program memory location 0 is written to. Bus Request and Bus Grant The ADSP-2186L can relinquish control of the data and ad- dress buses to an external device. When the external device requires access to memory, it asserts the bus request (BR) sig- nal. If the ADSP-2186L is not performing an external memory access, it responds to the active BR input in the following pro- cessor cycle by: • Three-stating the data and address buses and the PMS, DMS, BMS, CMS, IOMS, RD, WR output drivers, • Asserting the bus grant ( BG) signal, and • Halting program execution. |
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